Results 1 to 10 of about 30,664 (252)
A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements [PDF]
The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on
Jakub Szyduczyński +2 more
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Time to digital converter (TDC) is a key block for time-gated single photon avalanche diode (SPAD) arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that
Mahdi Rezvanyvardom +2 more
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High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip
This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and
Hai Wang, Min Zhang, Yan Liu
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This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively.
Mengdi Zhang +3 more
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Linearity improvement of UltraScale+ FPGA-based time-to-digital converter
Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement.
Jaewon Kim +4 more
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Analysis and Design of a New Voltage Amplifier Applying In The Time and Voltage Domain Converters [PDF]
In this paper a new voltage amplifier is investigated which is employed in the time and voltage domain converters such as analog to digital converters (ADCs) and time to digital converters (TDCs).
نازنین معلمیان +2 more
doaj +1 more source
Technology Independent ASIC Based Time to Digital Converter
This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces ...
Rui Machado +3 more
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An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation
This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated.
Daniel Junehee Lee +3 more
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PROCESS-ORIENTED SYNTHESIS OF SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS FOR INTEGRATED CIRCUITS [PDF]
Subject of Research. High-resolution successive approximation analog-to-digital converters include a digital-to-analog converter with multiple capacitor arrays and have significant nonlinearity.
A. A. Mikhteeva, N. V. Kolesov
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In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary ...
Li Wang +4 more
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