Results 21 to 30 of about 30,664 (252)

Impedance Characteristics and Harmonic Analysis of LCL-Type Grid-Connected Converter Cluster

Energies, 2022
This study addresses the output impedance model of the LCL-type grid-connected converter considering the dead-time effects and the digital control delay.
Xiaojie Zhou, Dezhi Xu, Yourui Huang
doaj   +1 more source

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs [PDF]

EAI Endorsed Transactions on Industrial Networks and Intelligent Systems, 2019
This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs).
Van-Thanh Ta, Van-Phuc Hoang, Xuan Tran   +2 more
doaj   +1 more source

All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

IEEE Access, 2019
Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET).
Rui Machado, Jorge Cabral, Filipe Serra Alves   +2 more
doaj   +1 more source

2D Vernier žiedinio laikinio skaitmeninio keitiklio modelis / The model of 2D Vernier time to digital converter based on gated ring oscillators

Mokslas: Lietuvos Ateitis, 2018
In this paper, the model of 2D Vernier time to digital converter (TDC) based on gated ring oscillators, which is implemented using VHDL hardware description language, is presented.
Marijan Jurgo, Romualdas Navickas
doaj   +1 more source

THE METHODOLOGY OF CIRCUIT CONSTRUCTION OF THE ANALOG VALUE CONVERTER IN THE TIMEFRAME

Измерение, мониторинг, управление, контроль, 2023
Background. Most modern digital voltmeters use an analog-to-digital converter (ADC) of the time-pulse type with two-stage integration, which takes place in two stages – integration and counting.
Mikhail A. Vatutin, Vitaliy P. Efimov, Evgeny V. Bormatov, Anton V. Zubkov   +3 more
doaj   +1 more source

Multivariable Unconstrained Pattern Search Method for Optimizing Digital PID Controllers Applied to Isolated Forward Converter

Energies, 2020
Most of the traditional PID tuning methods are heuristic in nature. The heuristic approach-based tuned PID controllers show only nominal performance.
Ghulam Abbas, Muhammad Usman Asad, Jason Gu, Salem Alelyani, Valentina E. Balas, Mohammad Rashid Hussain, Umar Farooq, Ahmed Bilal Awan, Ali Raza, Chunqi Chang   +9 more
doaj   +1 more source

A 0.6 V 4 GS/s −56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS

IEEE Access, 2022
A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling ...
Qian Chen, Chirn Chye Boon, Yuan Liang
doaj   +1 more source

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification [PDF]

Radioengineering, 2015
This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop).
M. Rezvanyvardom, E. Farshidi
doaj  

3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works

Sensors, 2021
Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications.
Jean-François Pratte, Frédéric Nolet, Samuel Parent, Frédéric Vachon, Nicolas Roy, Tommy Rossignol, Keven Deslandes, Henri Dautet, Réjean Fontaine, Serge A. Charlebois   +9 more
doaj   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source