PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks [PDF]
Recently, cyberattacks on Controller Area Network (CAN) which is one of the automotive networks are becoming a severe problem. CAN is a protocol for communicating among Electronic Control Units (ECUs) and it is a de-facto standard of automotive networks.
Shuji Ohira +3 more
openaire +2 more sources
Firmware-only implementation of time-to-digital converter (TDC) in field-programmable gate array (FPGA) [PDF]
A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array, (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter.
Wu, Jinyuan, Shi, Zonghan, Wang, Irena Y
openaire +2 more sources
This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 mus dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive ...
Antti Mäntyniemi +2 more
openaire +3 more sources
Nanosecond, Nanometer Movies of MEMS/NEMS Dynamics in a Standard SEM Using Time-Tagged Secondary Electrons. [PDF]
For the observation of micromechanical devices, a fast imaging technique with high temporal resolution is needed. Here, we demonstrate that a standard scanning electron microscope can be converted into a time‐resolving instrument using a fast detector and a time‐to‐digital converter.
Rehmann J +4 more
europepmc +2 more sources
Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology. [PDF]
As a nanoscale computing paradigm, quantum-dot cellular automata (QCA) technology demonstrates significant advantages over conventional CMOS implementations, including improved device density, minimized power dissipation, and increased operational speed.
Modanlou S, Gholami M.
europepmc +2 more sources
From Sensing Mechanisms to System Co-Design: Graphene-Based Sensors and Readout Circuits. [PDF]
This review establishes a unified PS–EQ–RF framework linking graphene sensing mechanisms, native electrical outputs, and output‐specific readout circuits. Voltage‐, current‐, resistance‐, and capacitance‐type sensing systems are systematically classified to guide architecture selection, low‐noise design, system co‐design, and practical integration ...
Zhang J +5 more
europepmc +2 more sources
A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module
The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine ...
Büchele, Maximilian +6 more
openaire +3 more sources
High-Resolution Time-to-Digital Converters (Tdcs) with a Bidirectional Encoder
A high-resolution time-to-digital converter (TDC) based on wave union (four-edge WU A), dual-sampling, and sub-TDL methods is proposed and implemented in a 16-nm Xilinx UltraScale+ field-programmable gate array (FPGA). We combine WU and dual-sampling techniques to achieve a high resolution.
Wang, Yu +3 more
openaire +4 more sources
Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors ‡ [PDF]
Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase ...
Augusto Ronchini Ximenes +2 more
openaire +6 more sources
A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi [PDF]
We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron.
M. Bogdan +10 more
semanticscholar +1 more source

