Results 41 to 50 of about 118,706,258 (232)

A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator

IEEE Access, 2021
This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution.
Okko Jarvinen, Vishnu Unnikrishnan, Waqas Siddiqui, Teuvo Korhonen, Kimmo Koli, Kari Stadius, Marko Kosunen, Jussi Ryynanen   +7 more
doaj   +1 more source

CMOS single photon sensor with in-pixel TDC for Time-of-Flight applications

, 2013
A CMOS imager that combines single photon sensitivity with photon timing capabilities has been developed for Time-Of-Flight (TOF) measurements and for Time-Correlated Single-Photon Counting (TCSPC) applications.
LUSSANA, RUDI, TAMBORINI, DAVIDE, TOSI, ALBERTO, R. Lussana, S. Tisa, F. Zappa, F. Villa, B. Markovic, MARKOVIC, BOJAN, TISA, SIMONE, D. Bronzi, BRONZI, DANILO, ZAPPA, FRANCO, D. Tamborini, A. Tosi, VILLA, FEDERICA ALBERTA   +15 more
core   +1 more source

Self-Timed Ring Oscillator Based Time-to-Digital Converter: a 0.35μm CMOS Proof-of-Concept Prototype

, 2021
International audienceThis paper presents an ASIC test chip designed and fabricated in 0.35μm CMOS process to further confirm and evaluate the advantages of the time-to-digital converter (TDC) based on a self-timed ring oscillator (STRO).
Laurent Fesquet, Elissati, Oussama, El Hadbi, Assia, Fesquet, Laurent, Oussama Elissati, Assia El-Hadbi   +5 more
core   +1 more source

Multi-Channel FPGA Time-to-Digital Converter With 10 ps Bin and 40 ps FWHM

IEEE Transactions on Instrumentation and Measurement, 2022
We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least significant bit (LSB), 164- $\mu \text{s}$ full-scale range, and good ...
D. Portaluppi, K. Pasquinelli, I. Cusini, F. Zappa   +3 more
semanticscholar   +1 more source

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Journal of Electrical and Computer Engineering, 2014
We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL).
Chao Chen, Shengwei Meng, Zhenghuan Xia, Guangyou Fang, Hejun Yin   +4 more
doaj   +1 more source

Design and Analysis of a Multirate 5-bit High-Order 52 fs_rms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

IEEE Access, 2021
This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC).
Ahmad Mouri Zadeh Khaki, Ebrahim Farshidi, Karim Ansari Asl, Sawal Hamid Md Ali, Masuri Othman   +4 more
doaj   +1 more source

Time-to-Digital Converter IP-Core for FPGA at State of the Art

IEEE Access, 2021
The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time–Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs,
F. Garzetti, N. Corna, N. Lusardi, A. Geraci   +3 more
semanticscholar   +1 more source

Magnetoelectric Nanoparticles Enable Modulation of Cortical Networks by Low‐Intensity Static Magnetic Fields In Vitro

Advanced Science, EarlyView.
Neuromodulation strategies are increasingly needed to stimulate, restore, or replace altered neuronal activity in disease. Cobalt ferrite‐barium titanate (CFO–BTO) magnetoelectric nanoparticles convert low‐intensity static magnetic fields into local electrical modulation of cortical networks.
Nathalia Cancino‐Fuentes, Alejandro Suarez‐Perez, Elric Zhang, Hao Ye, Marta Bonato, Joana Covelo, Vitaly Pustovalov, Anton Guimera‐Brunet, Xavi Illa, Valentin Gantenbein, Cagatay M. Oral, Marta Parazzini, Salvador Pané, Maria V. Sanchez‐Vives   +13 more
wiley   +1 more source

An Adaptive-Resolution SAR ADC With Metastability-Sensing 1-bit TDC in 65-nm CMOS

IEEE Open Journal of Circuits and Systems
We propose a metastability-sensing one-bit time-to-digital converter (TDC) for a successive-approximation (SAR) analog-to-digital converter (ADC) that detects a metastability-specific current in the comparator, gates its clock to stop the conversion ...
Jorgen M. Sandvik, Trond Ytterdal
doaj   +1 more source

Implementation and development of a DAQ system DELILA at ELI-NP [PDF]

EPJ Web of Conferences
This paper reports the current status of the Data AcQuisition (DAQ) system in ELI-NP, Romania. The DAQ system uses several data-taking electronics modules, CAEN 1730 1725 and 1740 digitizer series, and Mesytec Analog-to-Digital Converter (ADC) and Time ...
Aogaki Sohichiroh, Niculae Stefan
doaj   +1 more source