Results 1 to 10 of about 18,884 (121)
A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC [PDF]
Sensors, 2021 This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources.
Jiyun Tong +5 more
doaj +5 more sources
Low-Jitter Clock Receivers for Fast Timing Applications [PDF]
SensorsPrecision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems.
Carl Grace +3 more
doaj +3 more sources
A Second-Order All-Digital TDC With Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops [PDF]
IEICE Transactions on Electronics, 2013 We present a small-area second-order all-digital time-todigital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by ...
Shintaro Izumi +2 more
exaly +3 more sources
A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Daniel O'Hare, Deepu John, Barry Cardiff
exaly +4 more sources
Low‐jitter DLL applied for two‐segment TDC
IET Circuits, Devices & Systems, 2017 A low‐jitter delay‐locked loop (DLL) for high‐resolution time‐to‐digital converter (TDC) is proposed in this study. The generated high accurate and low‐jitter outputs with uniformly distributed multiphase clocks directly from the voltage‐controlled delay line (VCDL) in DLL are applied to two‐segment TDC.
Jin Wu 0004 +5 more
openaire +3 more sources
Design of 16 × 16 Low-Timing-Jitter InGaAs/InP Single-Photon Avalanche Photodiode Array for LiDAR
IEEE Photonics JournalThe precise calibration of timing jitter in single-photon chips and LiDAR devices is critical for the development of high-precision LiDAR systems. This paper presents the design and fabrication of a double-diffused InGaAs/InP SAGCM single-photon ...
Yu Chang +7 more
doaj +2 more sources
ParticlesTiming measurements are critical for the detectors at the future HL-LHC, to resolve reconstruction ambiguity when the number of simultaneous interactions reaches up to 200 per bunch crossing.
Salah El Dine Hammoud
doaj +2 more sources
Applied SciencesAdder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection
Aoming Zhan +3 more
doaj +2 more sources
The Egyptian Journal of Otolaryngology, 2022 Objectives Dysphonia is a common compliant in hypothyroid patients. Subjective voice changes could be clearly found in congenital hypothyroid children (CHC); however, the early treated children with thyroid hormone replacement (THR) may not experience ...
Heba Mahmoud Farag +3 more
doaj +1 more source
MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution
Electronics, 2021 This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of ...
J. Mauricio +12 more
semanticscholar +1 more source