Results 21 to 30 of about 8,847,760 (170)
Investigation of first-order digital bang-bang phase-locked loops with reference clock jitter [PDF]
, 2008 Paper presented at the Nordic microelectronics conference (NORCHIP), Tallinn, Estonia, 17-18 November, 2008Bang-bang phase-locked loops (BBPLLs) are a class of PLLs with a binary-quantized phase detector (BPD).
Tertinek, Stefan +3 more
core +1 more source
, 2023 Timing jitter of a single-photon device is essential for determining the coherence properties of quantum light sources. However, Jitter measurements were often not performed at the ultra-diluted light level present for quantum light sources.
Matthias Nuß (14521622) +2 more
core +1 more source
Fluorescence Lifetime Imaging Techniques-A Review on Principles, Applications and Clinical Relevance. [PDF]
J BiophotonicsThis article gives an overview of the most frequently used fluorescence‐lifetime imaging (FLIM) techniques, their capabilities and typical applications in biology and clinical studies. ABSTRACT This article gives an overview of the most frequently used fluorescence‐lifetime imaging (FLIM) techniques, their capabilities, and typical applications ...
Shcheslavskiy VI +5 more
europepmc +2 more sources
Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops [PDF]
, 2009 Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump ...
Tertinek, Stefan +3 more
core +1 more source
A BIST circuit for random jitter measurement [PDF]
, 2012 textJitter is a dominant factor contributing to a high bit error rate (BER) in high speed I/O circuitry, and it aggravates the quality of a clock signal from a phase-locked loop (PLL), subsequently impacting a given timing budget.
Lee, Jae Wook
core +1 more source
A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links
, 2021 An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented.
Jongsun Kim, Sungwook Choi, Dongjun Park
core +1 more source
IEEE AccessThis paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho +9 more
doaj +1 more source
International Journal of Circuit Theory and Applications, Volume 54, Issue 11, Page 5185-5201, November 2026.A co‐designed implicit‐reset phase‐frequency detector (PFD) and nonlinear amplifier‐assisted charge pump (CP) achieve dead zone‐free operation from 10 MHz to 4.7 GHz with < 0.5% current mismatch without calibration, enabling −80 dBc of reference spur and 0.50 ps of RMS jitter in a 180 nm of CMOS PLL.
A. Ghaemnia +3 more
wiley +1 more source
, 2021 The advent of the next-generation wireless communication standards demands increasingly faster transceivers, posing extremely challenging requirements on the frequency-synthesizer integrated jitter [1, 2].
Parisi A. +13 more
core +2 more sources
Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization
International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5045-5061, October 2026.This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley +1 more source