Results 21 to 30 of about 535 (152)

A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

IEEE Access
The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff   +4 more
doaj   +2 more sources

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

IEEE Open Journal of the Solid-State Circuits Society
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers   +9 more
doaj   +2 more sources

Parallel PWMs based fully digital transmitter with wide carrier frequency range. [PDF]

ScientificWorldJournal, 2013
The carrier‐frequency (CF) and intermediate‐frequency (IF) pulse‐width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF‐PWM and precorrected CF‐PWM, a fully digital transmitter with unit‐delay autocalibration is implemented in ...
Zhou B, Zhang K, Zhou W, Zhang Y, Liu D.
europepmc   +2 more sources

Contributions to the analysis and design of an ADPLL [PDF]

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006
In this paper, we propose two contributions to the simulation and design of an All-Digital Phase-Locked Loop (ADPLL) for RF applications. First, we extend the behavioral model we already proposed, in order to include detailed fractional aspects. Second, we propose a new adaptive algorithm that can be integrated in this ADPLL in order to lower its ...
Cyril Joubert, Jean Francois Bercher, Genevieve Baudoin, Thierry Divel, Pierre Baudin   +4 more
openaire   +3 more sources

An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking

IEEE Access, 2021
This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman, Arash Hejazi, Imran Ali, Muhammad Asif, Seongjin Oh, Pervesh Kumar, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, Kang-Yoon Lee   +14 more
doaj   +1 more source

A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting

IEEE Access, 2021
This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the ...
Heon Hwa Cheong, Suhwan Kim
doaj   +1 more source

Design of a high‐performance advanced phase locked loop with high stability external loop filter

IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 1-12, January 2023., 2023
Abstract For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer
Kalpana Kasilingam, Paulchamy Balaiyah, Stephen Jeswinde Nuagah, Piyush Kumar Shukla   +3 more
wiley   +1 more source

A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control

Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021
Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun, Yushi Zhou, Zhanjun Bai, Yong Chen   +3 more
wiley   +1 more source

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Mathematical Problems in Engineering, Volume 2021, Issue 1, 2021., 2021
This research proposed the design and calculations of ultra‐low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF‐nMOS subthreshold or triode region to achieve ultra‐
Muhammad Ovais Akhter, Najam Muhammad Amin, Dazhong Ma   +2 more
wiley   +1 more source

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL [PDF]

IEEE Journal of Solid-State Circuits, 2021
This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which
Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski   +4 more
openaire   +1 more source