Results 21 to 30 of about 132 (116)
IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
doaj +1 more source
A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting
IEEE Access, 2021 This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the ...
Heon Hwa Cheong, Suhwan Kim
doaj +1 more source
Design of a high‐performance advanced phase locked loop with high stability external loop filter
IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 1-12, January 2023., 2023 Abstract For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer
Kalpana Kasilingam +3 more
wiley +1 more source
A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control
Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021 Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun +3 more
wiley +1 more source
Mathematical Problems in Engineering, Volume 2021, Issue 1, 2021., 2021 This research proposed the design and calculations of ultra‐low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF‐nMOS subthreshold or triode region to achieve ultra‐
Muhammad Ovais Akhter +2 more
wiley +1 more source
Design of novel hybrid - digitally controlled oscillator for ADPLL
Memories - Materials, Devices, Circuits and Systems, 2023 Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input.
Mohd Ziauddin Jahangir +1 more
doaj +1 more source
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL [PDF]
IEEE Journal of Solid-State Circuits, 2021 This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which
Jianglin Du +4 more
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IEEE Access, 2021 An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper.
Jen-Chieh Liu, Yu-Ping Li
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Master‐Slave Topologies with Phase‐Locked Loops
Wireless Communications and Mobile Computing, Volume 2020, Issue 1, 2020., 2020 Since phase‐locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids ...
José Roberto C. Piqueira +1 more
wiley +1 more source
A Scalable DCO Design for Portable ADPLL Designs [PDF]
2005 IEEE International Symposium on Circuits and Systems, 2005 A novel digital controlled oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly.
Chia-Tsun Wu +3 more
openaire +2 more sources