Results 21 to 30 of about 133 (118)

A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

IEEE Access, 2019
This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less ...
Na Yan, Lei Ma, Yongxin Xu, Sizheng Chen, Xusong Liu, Junhui Xiang, Hao Min   +6 more
doaj   +1 more source

A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class‐C DCO

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption.
Lei Ma, Na Yan, Sizheng Chen, Yangzi Liu, Hao Min, Chaojiang Li   +5 more
wiley   +1 more source

An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

IEEE Access, 2020
In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is ...
Imran Ali, Hamed Abbasizadeh, Muhammad Riaz Ur Rehman, Muhammad Asif, Seong Jin Oh, Young Gun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee   +9 more
doaj   +1 more source

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved.
Sizheng Chen, Tingting Shi, Lei Ma, Cheng Kang, Na Yan, Hao Min, Christian Fager   +6 more
wiley   +1 more source

Digital Closed‐Loop Driving Technique Using the PFD‐Based CORDIC Algorithm for a Biaxial Resonant Microaccelerometer

Journal of Sensors, Volume 2017, Issue 1, 2017., 2017
A digital closed‐loop driving technique is presented in this paper that uses the PFD‐ (phase frequency detector‐) based CORDIC (coordinate rotation digital computer) algorithm for a biaxial resonant microaccelerometer. A conventional digital closed‐loop self‐oscillation system based on the CORDIC algorithm is implemented and simulated using Simulink ...
Bo Yang, Lei Wu, Binlong Wang, Qiuhua Wang, Francesco Dell’Olio   +4 more
wiley   +1 more source

CMOS time‐to‐digital converters for mixed‐mode signal processing

The Journal of Engineering, Volume 2014, Issue 4, Page 140-154, April 2014., 2014
This study provides an in‐depth review of the principles, architectures and design techniques of CMOS time‐to‐digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs.
Fei Yuan
wiley   +1 more source

FPGA‐Based Implementation of All‐Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

International Journal of Reconfigurable Computing, Volume 2014, Issue 1, 2014., 2014
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed‐loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types ...
Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang, Nadia Nedjah   +5 more
wiley   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays

IEEE Access, 2018
In this paper, we introduce a reconfigurable oscillatory network that generates a synchronous and distributed clocking signal. We propose an accurate model of the network to facilitate the study of its design space and ensure that it operates in its ...
Eugene Koskin, Dimitri Galayko, Elena Blokhina   +2 more
doaj   +1 more source

480 MHz 10‐tap Clock Generator Using Edge‐Combiner DLL for USB 2.0 Applications

Journal of Electrical and Computer Engineering, Volume 2012, Issue 1, 2012., 2012
A clock generator with an edge‐combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10‐tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL.
Takashi Kawamoto, Kazuhiro Ueda, Takayuki Noto, Woogeun Rhee   +3 more
wiley   +1 more source