Results 11 to 20 of about 535 (152)

FPGA Based Modelling of an ADPLL Network [PDF]

2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019
This paper introduces and compares the implementation of a number of FPGA based ADPLL network prototyping architectures. Networks are then created using three different ADPLL implementations and tests performed on each. Based on these test results, comparison is made to both the expected performance and role of each ADPLL design as a development tool.
Elena Blokhina, D Galayko
exaly   +5 more sources

Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL

IEEE Access
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
exaly   +4 more sources

Time-Domain ADPLL BPSK, QPSK, and 8PSK Demodulators

Journal of Electrical and Computer Engineering
Time-domain all-digital-phase-locked-loop phase-shift-keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low-voltage nanoscale CMOS techology.
Phanumas Khumsat, Thanabodee Koyphol, Tan Thongruk, Tidarat Inyod   +3 more
doaj   +3 more sources

An analysis of ADPLL applications in various fields

Indonesian Journal of Electrical Engineering and Computer Science, 2020
<span>ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and
R. Dinesh, Ramalatha Marimuthu
openaire   +5 more sources

A Review on Micro-Watts All-Digital Frequency Synthesizers [PDF]

Micromachines
This paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications.
Venkadasamy Navaneethan, Boon Chiat Terence Teo, Annamalai Arasu Muthukumaraswamy, Xian Yang Lim, Liter Siek   +4 more
doaj   +2 more sources

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

SN Applied Sciences, 2022
This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented ...
Huirem Bharat Meitei, Manoj Kumar
exaly   +2 more sources

An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications [PDF]

Sensors
To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully
Nam-Seog Kim
doaj   +2 more sources

Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology [PDF]

Scientific Reports
As a nanoscale computing paradigm, quantum-dot cellular automata (QCA) technology demonstrates significant advantages over conventional CMOS implementations, including improved device density, minimized power dissipation, and increased operational speed.
Shahram Modanlou, Mohammad Gholami
doaj   +2 more sources

An Interpolated Flying-Adder-Based Frequency Synthesizer

Journal of Electrical and Computer Engineering, 2011
This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle ...
Pao-Lung Chen, Chun-Chien Tsai
doaj   +2 more sources

FPGA implementation of reconfigurable ADPLL network for distributed clock generation [PDF]

2011 International Conference on Field-Programmable Technology, 2011
This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described.
Shan, Chuan, Zianbetov, Eldar, Javidan, Mohammad, Anceau, François, Terosiet, Mehdi, Feruglio, Sylvain, Galayko, Dimitri, Romain, Olivier, Colinet, Eric, Juillard, Jérome   +9 more
openaire   +3 more sources