Results 1 to 10 of about 275 (117)
ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW
Jurnal Teknologi, 2021 An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology.
S. N. Ishak +3 more
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DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW [PDF]
Jurnal Teknologi, 2019 Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology.
Choong, Florence +6 more
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An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications [PDF]
SensorsTo establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully
Nam-Seog Kim
doaj +2 more sources
An Interpolated Flying-Adder-Based Frequency Synthesizer
Journal of Electrical and Computer Engineering, 2011 This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle ...
Pao-Lung Chen, Chun-Chien Tsai
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IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
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A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting
IEEE Access, 2021 This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the ...
Heon Hwa Cheong, Suhwan Kim
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FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter
SN Applied Sciences, 2022 This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented ...
Huirem Bharat Meitei, Manoj Kumar
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IEEE Access, 2021 An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper.
Jen-Chieh Liu, Yu-Ping Li
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A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications
IEEE Access, 2019 This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less ...
Na Yan +6 more
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A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen +4 more
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