Results 41 to 50 of about 74 (65)
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Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)

Journal of Circuits, Systems and Computers, 2021
Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is
Vikas Balikai, Harish Kittur
openaire   +1 more source

Single-Event Characterization of Bang-bang All-digital Phase-locked Loops (ADPLLs)

IEEE Transactions on Nuclear Science, 2015
The single-event vulnerability of a bang-bang ADPLL is investigated through fault injection experiments and circuit simulations. Single-event upsets in the digital loop filter result in the worst-case error response of the ADPLL, often requiring phase reacquisition.
Y. P. Chen   +7 more
openaire   +1 more source

A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558), 2002
In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process.
null Kuo-Hsing Cheng, null Yu-Jung Chen
openaire   +1 more source

Single-Event Characterization of Common 1<formula> <tex>$^{\hbox{st}}$</tex> </formula> and 2<formula> <tex>$^{\hbox{nd}}$</tex> </formula>-order All-digital Phase-locked Loops (ADPLLs)

IEEE Transactions on Nuclear Science, 2017
Yanran P. Chen   +5 more
openaire   +1 more source

All digital phase locked loop (ADPLL) with frequency locked loop

2020
MOEHLMANN ULRICH   +2 more
openaire   +2 more sources

Design and Implementation of a Digital Phase Frequency Detector for All Digital Phase Locked Loops (ADPLL)

2025 IEEE International Microwave and Antenna Symposium (IMAS)
Mahmoud Desoky   +2 more
openaire   +1 more source

Design and Comparative Analysis of an All-Digital Phase-Locked Loop (ADPLL) across CMOS Technology Nodes

2026 8th International Conference on Devices, Circuits, and Systems (ICDCS)
Harshith Varma Rudra Raju, Papanasam E
openaire   +1 more source

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