Results 41 to 50 of about 275 (117)
Nonlinearity-Induced Spur Analysis in Fractional-
IEEE Open Journal of the Solid-State Circuits SocietyA fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu +2 more
doaj +1 more source
, 2022 5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum.
Zhang, Xiaomeng
core
Linearity Calibration Method for Stochastic Time-to-Digital Converters
IEEE AccessStochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj +1 more source
A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices [PDF]
A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study.
Kihara, Takao +5 more
core +1 more source
Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications [PDF]
, 2012 This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the ...
Dash, Suraj, Das, Abhishek
core
The Implementation and Analysis of an All-digital Phase-locked Loop
, 2012 [[abstract]]An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time.
Chen, Po-Yueh; Su, Hung-Lung
core
A 5.4 GHZ All-Digital Phase-Locked Loop with a wide output swing and high-linearity DAC
, 2014 A 5.4 GHz All-Digital Phase-Locked Loop (ADPLL) is presented in this paper. The ADPLL is designed in 65nm CMOS process. A 7 bit wide output swing and high linearity digital-to-analog converter (DAC) is used in this ADPLL to achieve good jitter ...
Gai, Weixin, Liu, Li, Li Liu, Weixin Gai
core +1 more source
Design and Implementation of an All Digital Phase Lock Loop
, 2007 In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits.
Tsai, Sheng-Chung, 蔡勝中
core
A 5GHz 90-nm CMOS all digital phase-locked loop
, 2010 An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time.
Ping Lu +3 more
core +1 more source
, 2022 This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC).
Kim, Hyojun +5 more
core +1 more source