Results 41 to 50 of about 55,100,936 (115)
A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL
IEEE Open Journal of the Solid-State Circuits SocietyThis article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang +9 more
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Design and Emulation of All-Digital Phase-Locked Loop on FPGA
, 2019 This paper demonstrates the design and implementation of an all-digital phase-locked loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique to show the feasibility and effectiveness of the ADPLL in the early design ...
Saichandrateja Radhapuram +2 more
core +1 more source
The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock [PDF]
, 2010 The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture. In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency ...
江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan +2 more
core +1 more source
IEEE AccessThis article presents a bridge IC with programmable DQS/WCK pattern generation and RDQS error detection that reduces the number of high-speed automatic test equipment (ATE) channels required for validating next-generation mobile memory interfaces.
Jaekwang Yun, Chan-Ho Kye
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Design and Implementation of an All Digital Phase Locked Loop using a Pulse Output Direct Digital Frequency Synthesizer [PDF]
, 2004 Phase Locked Loops (PLLs) are widely used in clock recovery and frequency synthesis. Fully Digital PLLs are more suitable for the monolithic implementation with other circuits compared to the traditional implementations of the PLLs.
Gothandaraman, Akila
core
IEEE AccessThis paper presents a continuous-time bandpass delta-sigma time-to-digital converter (CT-BP $\Delta \Sigma $ TDC) for all-digital fractional- $N$ phase-locked loops (ADPLLs) operating under low reference frequency and wide loop bandwidth constraints ...
Thi Viet Ha Nguyen, Cong-Kha Pham
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Elimination of false-locking in long loop phase-locked receivers [PDF]
, 1982 Although long-loop phase-locked techniques are finding increasing application in the fields of mobile radio and satellite communications, their use has several drawbacks.
Sladen, JPH, McGeehan, JP
core
Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops [PDF]
, 2009 Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump ...
Tertinek, Stefan +3 more
core +1 more source
Nonlinearity-Induced Spur Analysis in Fractional-
IEEE Open Journal of the Solid-State Circuits SocietyA fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu +2 more
doaj +1 more source
Linearity Calibration Method for Stochastic Time-to-Digital Converters
IEEE AccessStochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj +1 more source