Results 21 to 30 of about 55,100,936 (115)

Digital Closed‐Loop Driving Technique Using the PFD‐Based CORDIC Algorithm for a Biaxial Resonant Microaccelerometer

Journal of Sensors, Volume 2017, Issue 1, 2017., 2017
A digital closed‐loop driving technique is presented in this paper that uses the PFD‐ (phase frequency detector‐) based CORDIC (coordinate rotation digital computer) algorithm for a biaxial resonant microaccelerometer. A conventional digital closed‐loop self‐oscillation system based on the CORDIC algorithm is implemented and simulated using Simulink ...
Bo Yang, Lei Wu, Binlong Wang, Qiuhua Wang, Francesco Dell’Olio   +4 more
wiley   +1 more source

CMOS time‐to‐digital converters for mixed‐mode signal processing

The Journal of Engineering, Volume 2014, Issue 4, Page 140-154, April 2014., 2014
This study provides an in‐depth review of the principles, architectures and design techniques of CMOS time‐to‐digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs.
Fei Yuan
wiley   +1 more source

FPGA‐Based Implementation of All‐Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

International Journal of Reconfigurable Computing, Volume 2014, Issue 1, 2014., 2014
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed‐loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types ...
Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang, Nadia Nedjah   +5 more
wiley   +1 more source

DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP

, 2016
The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL.
Anupama Patil*, Dr P.H.Tandel
core   +1 more source

ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP [PDF]

A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented.
Wang, Weimin, Radhapuram, Saichandrateja, Bae, Jungnam, Jo, Ikkyun, Matsuoka, Toshimasa   +4 more
core   +1 more source

480 MHz 10‐tap Clock Generator Using Edge‐Combiner DLL for USB 2.0 Applications

Journal of Electrical and Computer Engineering, Volume 2012, Issue 1, 2012., 2012
A clock generator with an edge‐combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10‐tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL.
Takashi Kawamoto, Kazuhiro Ueda, Takayuki Noto, Woogeun Rhee   +3 more
wiley   +1 more source

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

VLSI Design, Volume 2012, Issue 1, 2012., 2012
This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all‐digital dual‐loop delay‐ and frequency‐locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA ...
Maher Assaad, Mohammed H. Alser, Antonio G. M. Strollo   +2 more
wiley   +1 more source

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

IEEE Access
In recent years, frequency-modulated continuous-wave (FMCW) radars have been widely used in the automotive field to measure the relative distance and speed of external targets.
Mengwei Yang, Jinyou Chen, Changhong Shan   +2 more
doaj   +1 more source

Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu, Woogeun Rhee, Zhihua Wang, Sudhakar Pamarti   +3 more
wiley   +1 more source

Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL

IEEE Access
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
doaj   +1 more source