Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]
Sensors (Basel), 2022 Lai WC.
europepmc +1 more source
Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]
Sensors (Basel), 2021 Sheng D, Chen WY, Huang HT, Tai L.
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Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing. [PDF]
Philos Trans A Math Phys Eng Sci, 2020 Miao L, Gao B, Li H, Tian G.
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ALL Digital Phase-Locked Loop (ADPLL): A Survey
International Journal of Future Computer and Communication, 2013 Kusum Lata, Manoj Kumar
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NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]
Sensors (Basel), 2020 Borejko T +11 more
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A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix. [PDF]
Sensors (Basel), 2017 Zhang M, Wang H, Liu Y.
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Parallel PWMs based fully digital transmitter with wide carrier frequency range. [PDF]
ScientificWorldJournal, 2013 Zhou B, Zhang K, Zhou W, Zhang Y, Liu D.
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Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype. [PDF]
Front Neurosci, 2018 Liu C +10 more
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A Review on Micro-Watts All-Digital Frequency Synthesizers. [PDF]
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An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [PDF]
Sensors (Basel)Nguyen TVH, Pham CK.
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