Results 11 to 20 of about 74 (65)

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

IEEE Access
In recent years, frequency-modulated continuous-wave (FMCW) radars have been widely used in the automotive field to measure the relative distance and speed of external targets.
Mengwei Yang, Jinyou Chen, Changhong Shan   +2 more
doaj   +1 more source

Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL

IEEE Access
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
doaj   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

IEEE Open Journal of the Solid-State Circuits Society
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski   +3 more
doaj   +1 more source

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

IEEE Open Journal of the Solid-State Circuits Society
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers   +9 more
doaj   +1 more source

A Bridge IC With Programmable DQS/WCK Pattern Generation and RDQS Error Detection for Next-Generation Mobile Memory Interface Testing

IEEE Access
This article presents a bridge IC with programmable DQS/WCK pattern generation and RDQS error detection that reduces the number of high-speed automatic test equipment (ATE) channels required for validating next-generation mobile memory interfaces.
Jaekwang Yun, Chan-Ho Kye
doaj   +1 more source

A 10 mW 3.2 GHz All-Digital Fractional-N PLL Achieving −120-dBc/Hz In-Band Phase Noise Using a Continuous Time Bandpass Delta–Sigma Time-to-Digital Converter in 180-nm CMOS

IEEE Access
This paper presents a continuous-time bandpass delta-sigma time-to-digital converter (CT-BP $\Delta \Sigma $ TDC) for all-digital fractional- $N$ phase-locked loops (ADPLLs) operating under low reference frequency and wide loop bandwidth constraints ...
Thi Viet Ha Nguyen, Cong-Kha Pham
doaj   +1 more source

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

IEEE Open Journal of the Solid-State Circuits Society
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski   +2 more
doaj   +1 more source

Linearity Calibration Method for Stochastic Time-to-Digital Converters

IEEE Access
Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj   +1 more source