Results 11 to 20 of about 275 (117)

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

IEEE Open Journal of the Solid-State Circuits Society
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski   +3 more
doaj   +2 more sources

Parallel PWMs based fully digital transmitter with wide carrier frequency range. [PDF]

ScientificWorldJournal, 2013
The carrier‐frequency (CF) and intermediate‐frequency (IF) pulse‐width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF‐PWM and precorrected CF‐PWM, a fully digital transmitter with unit‐delay autocalibration is implemented in ...
Zhou B, Zhang K, Zhou W, Zhang Y, Liu D.
europepmc   +2 more sources

Design of a high‐performance advanced phase locked loop with high stability external loop filter

IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 1-12, January 2023., 2023
Abstract For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer
Kalpana Kasilingam, Paulchamy Balaiyah, Stephen Jeswinde Nuagah, Piyush Kumar Shukla   +3 more
wiley   +1 more source

A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control

Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021
Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun, Yushi Zhou, Zhanjun Bai, Yong Chen   +3 more
wiley   +1 more source

Master‐Slave Topologies with Phase‐Locked Loops

Wireless Communications and Mobile Computing, Volume 2020, Issue 1, 2020., 2020
Since phase‐locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids ...
José Roberto C. Piqueira, Pierre-Martin Tardif   +1 more
wiley   +1 more source

A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class‐C DCO

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption.
Lei Ma, Na Yan, Sizheng Chen, Yangzi Liu, Hao Min, Chaojiang Li   +5 more
wiley   +1 more source

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved.
Sizheng Chen, Tingting Shi, Lei Ma, Cheng Kang, Na Yan, Hao Min, Christian Fager   +6 more
wiley   +1 more source

Digital Closed‐Loop Driving Technique Using the PFD‐Based CORDIC Algorithm for a Biaxial Resonant Microaccelerometer

Journal of Sensors, Volume 2017, Issue 1, 2017., 2017
A digital closed‐loop driving technique is presented in this paper that uses the PFD‐ (phase frequency detector‐) based CORDIC (coordinate rotation digital computer) algorithm for a biaxial resonant microaccelerometer. A conventional digital closed‐loop self‐oscillation system based on the CORDIC algorithm is implemented and simulated using Simulink ...
Bo Yang, Lei Wu, Binlong Wang, Qiuhua Wang, Francesco Dell’Olio   +4 more
wiley   +1 more source

CMOS time‐to‐digital converters for mixed‐mode signal processing

The Journal of Engineering, Volume 2014, Issue 4, Page 140-154, April 2014., 2014
This study provides an in‐depth review of the principles, architectures and design techniques of CMOS time‐to‐digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs.
Fei Yuan
wiley   +1 more source

FPGA‐Based Implementation of All‐Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

International Journal of Reconfigurable Computing, Volume 2014, Issue 1, 2014., 2014
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed‐loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types ...
Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang, Nadia Nedjah   +5 more
wiley   +1 more source