Results 11 to 20 of about 55,100,936 (115)
Parallel PWMs based fully digital transmitter with wide carrier frequency range. [PDF]
ScientificWorldJournal, 2013 The carrier‐frequency (CF) and intermediate‐frequency (IF) pulse‐width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF‐PWM and precorrected CF‐PWM, a fully digital transmitter with unit‐delay autocalibration is implemented in ...
Zhou B, Zhang K, Zhou W, Zhang Y, Liu D.
europepmc +2 more sources
Design of a high‐performance advanced phase locked loop with high stability external loop filter
IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 1-12, January 2023., 2023 Abstract For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer
Kalpana Kasilingam +3 more
wiley +1 more source
A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control
Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021 Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun +3 more
wiley +1 more source
Phase Locked Loop Test Methodology [PDF]
, 2008 Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based.
Burbidge, Martin, Richardson, Andrew
core +4 more sources
Master‐Slave Topologies with Phase‐Locked Loops
Wireless Communications and Mobile Computing, Volume 2020, Issue 1, 2020., 2020 Since phase‐locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids ...
José Roberto C. Piqueira +1 more
wiley +1 more source
Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter [PDF]
, 2011 Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several ...
Tertinek, Stefan +3 more
core +1 more source
Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications [PDF]
, 2022 5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum.
Zhang, Xiaomeng
core +1 more source
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction [PDF]
, 2014 This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate
Staszewski, Robert Bogdan +3 more
core +3 more sources
A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class‐C DCO
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018 This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption.
Lei Ma +5 more
wiley +1 more source
A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018 A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved.
Sizheng Chen +6 more
wiley +1 more source