Results 1 to 10 of about 362 (147)
Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation [PDF]
Sensors, 2021 This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing
Duo Sheng +3 more
doaj +5 more sources
Technologies, 2021 This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology.
Santthosh Selvaraj +2 more
doaj +4 more sources
Applied Sciences, 2021 This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system.
Min-Su Kim, Sang-Sun Yoo
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An optimized DCO with modified binary-weighted DCTLs based hybrid tuning banks for an E-band DPLL [PDF]
Scientific ReportsAn optimized millimeter-wave digital controlled oscillator (DCO) in a 40-nm CMOS process is presented in this work. The coarse-tuning modules and medium-tuning modules of the DCO utilize modified binary-weighted digitally controlled transmission lines ...
Lu Tang +6 more
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An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications [PDF]
SensorsTo establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully
Nam-Seog Kim
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IEEE Access, 2021 An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper.
Jen-Chieh Liu, Yu-Ping Li
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IEEE Access, 2022 This paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock.
Minuk Heo +4 more
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IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
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A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems
IEEE Access, 2022 An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented.
Junghoon Jin, Seungjun Kim, Jongsun Kim
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IEEE Access, 2021 This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output
Yoonjae Choi +6 more
doaj +1 more source