Results 41 to 50 of about 367 (152)

Push–pull mode digital control for LLC series resonant dc‐to‐dc converters

IET Power Electronics, Volume 8, Issue 11, Page 2115-2124, November 2015., 2015
This study presents the design and performance evaluation of the digital control adapted to an LLC series resonant dc‐to‐dc converter operating with wide input and load variations. The proposed control design correctly incorporates the wide‐varying power stage dynamics and variable small‐signal gain of a digitally controlled oscillator, thereby ...
Syam K. Pidaparthy, Jinhaeng Jang, Byungcho Choi   +2 more
wiley   +1 more source

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

VLSI Design, Volume 2012, Issue 1, 2012., 2012
This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all‐digital dual‐loop delay‐ and frequency‐locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA ...
Maher Assaad, Mohammed H. Alser, Antonio G. M. Strollo   +2 more
wiley   +1 more source

Implementation of an All-digital Phase-locked Loop Using a New DCO [PDF]

, 2012
[[abstract]]A novel digitally controlled oscillator (DCO) is implemented for All-digital phase lock loop (ADPLL) applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the ...
Chen, Po-Yueh; Su, Hung-Lung
core  

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

RGB‐Single‐Chip OLEDs for High‐Speed Visible‐Light Communication by Wavelength‐Division Multiplexing

Advanced Science, Volume 11, Issue 47, December 18, 2024.
High‐speed red, green, and blue organic light‐emitting diodes (RGB‐OLEDs) are integrated onto a single substrate and achieve a record data transmission rate for an OLED transmitter system of 3.2 Gbps by exploiting wavelength‐division multiplexing. It is demonstrated that integrating RGB pixels is a useful way to increase the data transmission rate of ...
Kou Yoshida, Cheng Chen, Harald Haas, Graham A. Turnbull, Ifor D. W. Samuel   +4 more
wiley   +1 more source

Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu, Woogeun Rhee, Zhihua Wang, Sudhakar Pamarti   +3 more
wiley   +1 more source

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process [PDF]

, 2020
International audienceThe immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications.
Bisiaux, Pierre, Siriburanon, Teerachot, Elena Blokhina, Pierre Bisiaux, Teerachot Siriburanon, Blokhina, Elena, Koskin, Eugene, Dimitri Galayko, Galayko, Dimitri, Eugene Koskin   +9 more
core   +1 more source

The Effect of Intermittent Signal on the Performance of Code Tracking Loop in GNSS Receivers

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper analyzes the code tracking performance in the presence of signal blanking in Global Navigation Satellite System (GNSS). The blanking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal blanking is used to remove random or periodic interference.
Chung-Liang Chang, Tzi-Dar Chiueh
wiley   +1 more source

A digitally controlled 2.4GHz CMOS oscillator [PDF]

, 2007
In this thesis work, a digitally controlled oscillator (DCO) is designed and implemented in a 65nm 6-metal CMOS technology with 1.2 supply voltage, along with a differential-to-single-ended converter and auxiliary digital on-chip circuitry for testing ...
Xu, Liangge
core  

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning [PDF]

, 2010
A digitally controlled oscillator (DCO) that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair ...
FANORI, LUCA, CASTELLO, RINALDO, LISCIDINI, ANTONIO, Antonio Liscidini, Rinaldo Castello, Luca Fanori   +5 more
core   +1 more source