Results 41 to 50 of about 362 (147)

Open‐Loop Wide‐Bandwidth Phase Modulation Techniques

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti, Kenichi Okada   +3 more
wiley   +1 more source

A Noise-Insensitive High-Resolution Digitally Controlled Ring Oscillator with Multipoint-Tuning Technique

, 2012
An eight-phase digitally controlled ring oscillator that employs a multipoint-tuning technique is presented. The DCO fine-tuning is realized by multi-variable RC loads to improve frequency resolution and coupled-noise rejection by reducing DCO gain. With
Te Han, Lu Li, Gai, Wei-Xin, Liu, Li, Li Liu, Han, Te, Li, Lu, Wei-Xin Gai   +7 more
core   +1 more source

RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity

, 2018
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li, Donald Y. C. Lie, Chaojiang Li, Dixian Zhao, Christian Fager   +4 more
wiley   +1 more source

A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation

, 2011
International audienceThis paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted ...
Jerome Juillard, Anceau, François, Javidan, Mohammad, Eldar Zianbetov, Juillard, Jerome, Mohammad Javidan, Eric Colinet, Colinet, Eric, Francois Anceau, Galayko, Dimitri, Dimitri Galayko, Zianbetov, Eldar   +11 more
core   +1 more source

A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator [PDF]

We present a low-voltage digitally-controlled oscillator (DCO) with the third-order ΔΣ modulator utilized in the medical implant communication service (MICS) frequency band. An optimized DCO core operating in the subthreshold region is designed, based on
Kihara, Takao, Bae, Jungnam, Radhapuram, Saichandrateja, Jo, Ikkyun, Matsuoka, Toshimasa   +4 more
core   +1 more source

A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS

IEEE Access
This paper presents a broadband optical receiver that employs multiple bandwidth extension techniques in analog front-end (AFE) and has efficient digital clock and data recovery (CDR). The AFE is implemented exclusively with inverter-based stages.
Hyungryul Kang, Inhyun Kim, Ruida Liu, Ankur Kumar, Il-Min Yi, Yuan Yuan, Zhihong Huang, Samuel Palermo   +7 more
doaj   +1 more source

A High Frequency Resolution Digitally Controlled Oscillator With Differential Tapped Inductor

, 2015
a novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array within the taps for fine frequency ...
Junhua Liu, Runhua Wang, Huailin Liao, Yang, Fan, Liao, Huailin, Wang, Runhua, Liu, Xiaozhe, Liu, Junhua, Xiaozhe Liu, Fan Yang   +9 more
core   +1 more source

Multiphase Digitally Controlled Oscillator for Future 5G Phased Arrays in 90 nm CMOS

, 2017
This paper reports a low noise Digitally Controlled Oscillator (DCO) with multiphase outputs, suitable for next generation phased arrays. The DCO core is implemented using an 8 stage Rotary Traveling Wave Oscillator (RTWO) topology.
Vigilante, Marco, Devos, Arnout, Reynaert, Patrick   +2 more
core   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

A 5.9 GHz LC-based digitally controlled oscillator with high frequency resolution using novel varactor pairs

, 2009
This paper reports an LC-based digitally controlled oscillator (DCO) using novel varactor pairs. Proposed DCO has high frequency resolution with low phase noise in 5.9 GHz.
Hong-Joo Song, Hyung-Joun Yoo, Choi, Yong-Chang, Yoo, Hyung-Joun, Sang-Sun Yoo, Song, Hong-Joo, Yoo, Sang-Sun, Yong-Chang Choi   +7 more
core   +1 more source