Results 41 to 50 of about 2,447,169 (147)
Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation
Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011 This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu +3 more
wiley +1 more source
The Effect of Intermittent Signal on the Performance of Code Tracking Loop in GNSS Receivers
Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011 This paper analyzes the code tracking performance in the presence of signal blanking in Global Navigation Satellite System (GNSS). The blanking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal blanking is used to remove random or periodic interference.
Chung-Liang Chang, Tzi-Dar Chiueh
wiley +1 more source
, 2023 Nowadays, in the world of high-performance computing, saving energy when great computing power is not needed is a must-to-have feature. This usually involves the implementation of Power Management Systems (PMS) to apply power saving polices such as ...
S. Saponara +4 more
core +1 more source
Open‐Loop Wide‐Bandwidth Phase Modulation Techniques
Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011 The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi +3 more
wiley +1 more source
RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity
, 2018 Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li +4 more
wiley +1 more source
A digitally controlled 2.4GHz CMOS oscillator
, 2007 In this thesis work, a digitally controlled oscillator (DCO) is designed and implemented in a 65nm 6-metal CMOS technology with 1.2 supply voltage, along with a differential-to-single-ended converter and auxiliary digital on-chip circuitry for testing ...
Xu, Liangge
core +1 more source
A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS
IEEE AccessThis paper presents a broadband optical receiver that employs multiple bandwidth extension techniques in analog front-end (AFE) and has efficient digital clock and data recovery (CDR). The AFE is implemented exclusively with inverter-based stages.
Hyungryul Kang +7 more
doaj +1 more source
IEEE AccessThis paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho +9 more
doaj +1 more source
A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation
, 2011 International audienceThis paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted ...
Jerome Juillard +11 more
core +1 more source
Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process
, 2020 International audienceThe immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications.
Bisiaux, Pierre +9 more
core +1 more source