Results 31 to 40 of about 2,447,169 (147)

A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class‐C DCO

open access: yesWireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption.
Lei Ma   +5 more
wiley   +1 more source

A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

open access: yesIEEE Access, 2019
This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less ...
Na Yan   +6 more
doaj   +1 more source

Past Results, Present Trends, and Future Challenges in Intrabody Communication

open access: yesWireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
Intrabody communication (IBC) is a wireless communication technology using the human body to develop body area networks (BANs) for remote and ubiquitous monitoring. IBC uses living tissues as a transmission medium, achieving power‐saving and miniaturized transceivers, making communications more robust against external interference and attacks on the ...
David Naranjo-Hernández   +5 more
wiley   +1 more source

Push–pull mode digital control for LLC series resonant dc‐to‐dc converters

open access: yesIET Power Electronics, Volume 8, Issue 11, Page 2115-2124, November 2015., 2015
This study presents the design and performance evaluation of the digital control adapted to an LLC series resonant dc‐to‐dc converter operating with wide input and load variations. The proposed control design correctly incorporates the wide‐varying power stage dynamics and variable small‐signal gain of a digitally controlled oscillator, thereby ...
Syam K. Pidaparthy   +2 more
wiley   +1 more source

Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars

open access: yes, 2021
This work presents the design of a 24-GHz digitally controlled oscillator (DCO) in an advanced 28-nm bulk CMOS technology for short-range frequency-modulated continuous-wave radar system-on-chip for mobile and Internet-of-Things devices.
Rengifo, Sammy Cerida   +9 more
core   +1 more source

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

open access: yesVLSI Design, Volume 2012, Issue 1, 2012., 2012
This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all‐digital dual‐loop delay‐ and frequency‐locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA ...
Maher Assaad   +2 more
wiley   +1 more source

Implementation of an All-digital Phase-locked Loop Using a New DCO [PDF]

open access: yes, 2012
[[abstract]]A novel digitally controlled oscillator (DCO) is implemented for All-digital phase lock loop (ADPLL) applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the ...
Chen, Po-Yueh; Su, Hung-Lung
core  

A Novel Low Power Digitally Controlled Oscillator with Improved linear Operating Range

open access: yes, 2011
In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters.
Mojtaba Lotfizad, Nasser Erfani Majd
core   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

open access: yesIEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon   +13 more
doaj   +1 more source

RGB‐Single‐Chip OLEDs for High‐Speed Visible‐Light Communication by Wavelength‐Division Multiplexing

open access: yesAdvanced Science, Volume 11, Issue 47, December 18, 2024.
High‐speed red, green, and blue organic light‐emitting diodes (RGB‐OLEDs) are integrated onto a single substrate and achieve a record data transmission rate for an OLED transmitter system of 3.2 Gbps by exploiting wavelength‐division multiplexing. It is demonstrated that integrating RGB pixels is a useful way to increase the data transmission rate of ...
Kou Yoshida   +4 more
wiley   +1 more source

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