Open‐Loop Wide‐Bandwidth Phase Modulation Techniques
Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011 The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi +3 more
wiley +1 more source
Low-Phase-Noise, High Switching Speed Digitally Controlled Ring Oscillator in 0.18 µm Complementary Metal Oxide Semiconductor [PDF]
, 2011 In this paper a 14-bit digitally controlled oscillator (DCO) with operating frequency up to 4.2 GHz in 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented.
Shashank Lingala +4 more
core +1 more source
RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity
, 2018 Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li +4 more
wiley +1 more source
A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM [PDF]
, 2008 A 5.4 GHz digitally controlled oscillator (DCO) has been implemented in a 90-nm CMOS process. It has three different frequency control words, coarse, medium, and fine. The coarse control bank uses MIM capacitors and differential MOS switches.
Henrik Sjoland +3 more
core +1 more source
A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator [PDF]
We present a low-voltage digitally-controlled oscillator (DCO) with the third-order ΔΣ modulator utilized in the medical implant communication service (MICS) frequency band. An optimized DCO core operating in the subthreshold region is designed, based on
Kihara, Takao +4 more
core +1 more source
Ultra-low-power Digitally-controlled Oscillator for Event-driven Transmitter [PDF]
, 2011 Event-driven wireless communication is a promising concept that presents new challenges to designers. For an event-driven transmitter, achieving high efficiency under the condition of ultra-low-power (ULP) consumption is one of the most critical tasks ...
Ba, A. (author)
core
A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS
IEEE AccessThis paper presents a broadband optical receiver that employs multiple bandwidth extension techniques in analog front-end (AFE) and has efficient digital clock and data recovery (CDR). The AFE is implemented exclusively with inverter-based stages.
Hyungryul Kang +7 more
doaj +1 more source
IEEE AccessThis paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho +9 more
doaj +1 more source
An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL [PDF]
, 2019 A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO ...
Park, HJ, Choi, KH, Sim, JY, Shin, JB
core +1 more source
Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars [PDF]
This work presents the design of a 24-GHz digitally controlled oscillator (DCO) in an advanced 28-nm bulk CMOS technology for short-range frequency-modulated continuous-wave radar system-on-chip for mobile and Internet-of-Things devices.
Rengifo, Sammy Cerida +4 more
core +1 more source