Results 11 to 20 of about 367 (152)
Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture [PDF]
, 2021 Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as ...
Igor Butryn +2 more
core +1 more source
IEEE Access, 2022 This paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock.
Minuk Heo +4 more
doaj +1 more source
Electronics Letters, Volume 58, Issue 7, Page 274-276, March 2022., 2022 Abstract The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability. A MASH2‐k FDC PLL architecture enabling (k + 2)th‐order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally ...
Ryoga Iwashita +3 more
wiley +1 more source
IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
doaj +1 more source
Low‐power multi‐band injection‐locked wireless receiver in 0.13 μm CMOS
IET Circuits, Devices &Systems, Volume 15, Issue 6, Page 522-539, September 2021., 2021 Abstract The design and analysis of a low‐power multi‐band injection‐locked wireless receiver, implemented in complementary metal–oxide–semiconductor (CMOS) 130 nm technology, for wireless sensor network (WSN) applications are presented. The proposed receiver composed of an injection‐locked oscillator (ILO), low‐noise amplifier (LNA), and an envelope ...
Jared Mercier, Yushi Zhou
wiley +1 more source
A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems
IEEE Access, 2022 An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented.
Junghoon Jin, Seungjun Kim, Jongsun Kim
doaj +1 more source
A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control
Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021 Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun +3 more
wiley +1 more source
IEEE Access, 2021 This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output
Yoonjae Choi +6 more
doaj +1 more source
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology [PDF]
, 2023 This work presents the design, in 28 nm CMOS technology, of an integrated LC-tank Digitally Controlled Oscillator (DCO) operating around 2 GHz with a wide tuning range between 1.24 GHz and 2.51 GHz.
G. Puccioni +5 more
core +1 more source
IEEE Access, 2020 In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is ...
Imran Ali +9 more
doaj +1 more source