Results 11 to 20 of about 2,447,169 (147)
A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS
This work investigates a 5.5–7.5‐GHz band‐configurable duty‐cycled wake‐up receiver (WuRX) fully implemented in a 45‐nm radio‐frequency (RF) silicon‐on‐insulator (SOI) complementary‐metal‐oxide‐semiconductor (CMOS) technology.
Rui Ma, Florian Protze, Frank Ellinger
doaj +2 more sources
Time-Domain ADPLL BPSK, QPSK, and 8PSK Demodulators
Time-domain all-digital-phase-locked-loop phase-shift-keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low-voltage nanoscale CMOS techology.
Phanumas Khumsat +3 more
doaj +2 more sources
DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW [PDF]
Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology.
Choong, Florence +6 more
openaire +4 more sources
A dual‐path signal‐superposition technique that can address issues which pose challenges in the designs of high speed I/Os with low electro‐magnetic interference/radiations (EMI/EMR) applications is proposed. This work demonstrates an output slew rate lower than 1 V/ns at data rate of hundreds of Mbps or above over PVT, without using huge on‐board ...
Xiaoyan Gui +6 more
wiley +1 more source
Abstract Direct RF sampling has been suggested as a solution for receivers that are flexible in frequency and across standards, while utilising only a single radio frequency front‐end. However there are concerns about their robustness in the presence of out‐of‐band and in‐band blockers.
Stephen Henthorn +2 more
wiley +1 more source
Abstract The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability. A MASH2‐k FDC PLL architecture enabling (k + 2)th‐order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally ...
Ryoga Iwashita +3 more
wiley +1 more source
Low‐power multi‐band injection‐locked wireless receiver in 0.13 μm CMOS
Abstract The design and analysis of a low‐power multi‐band injection‐locked wireless receiver, implemented in complementary metal–oxide–semiconductor (CMOS) 130 nm technology, for wireless sensor network (WSN) applications are presented. The proposed receiver composed of an injection‐locked oscillator (ILO), low‐noise amplifier (LNA), and an envelope ...
Jared Mercier, Yushi Zhou
wiley +1 more source
A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control
Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun +3 more
wiley +1 more source
High-Resolution mm-wave Digitally Controlled Oscillator in CMOS [PDF]
All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to ...
Wang, Yunqi
core +5 more sources
In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is ...
Imran Ali +9 more
doaj +1 more source

