Results 31 to 40 of about 275 (117)

The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock [PDF]

, 2010
The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture. In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency ...
江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan
core   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

A Low‐Power Digitally Controlled Oscillator for All Digital Phase‐Locked Loops

VLSI Design, Volume 2010, Issue 1, 2010., 2010
A low‐power and low‐jitter 12‐bit CMOS digitally controlled oscillator (DCO) design is presented. The Low‐Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters.
Jun Zhao, Yong-Bin Kim, Gregory D. Peterson   +2 more
wiley   +1 more source

All-digital RF phase-locked loops exploiting phase prediction

, 2017
This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate
Staszewski, Robert Bogdan, Zhuang, Jingcheng   +1 more
core   +2 more sources

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

, 2019
This paper demonstrates the design and implementation of an all-digital phase-locked loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique to show the feasibility and effectiveness of the ADPLL in the early design ...
Saichandrateja Radhapuram, Takuya Yoshihara, Toshimasa Matsuoka   +2 more
core   +1 more source

A 5GHz 90-nm CMOS all digital phase-locked loop

, 2009
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells.
Henrik Sjoland, Ping Lu, Sjöland, Henrik, Lu, Ping   +3 more
core   +1 more source

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

IEEE Open Journal of the Solid-State Circuits Society
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers   +9 more
doaj   +1 more source

An Low-Jitter All-Digital Phased-Locked Loop Using a Suppresive Digital Loop Filter

, 2012
[[abstract]]In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1 ps resolution.
Hsuan-Jung Hsu;Shi-Yu Huang
core   +1 more source

All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

, 2015
This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase ...
Tikka, Tero, Stadius, Kari, Tero Tikka, Jussi Ryynanen, Antonov, Yury, Yury Antonov, Kari Stadius, Ryynänen, Jussi   +7 more
core   +1 more source