Results 31 to 40 of about 74 (65)

Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology. [PDF]

Sci Rep
Modanlou S, Gholami M.
europepmc   +1 more source

CMOS Point-of-Care Diagnostics Technologies: Recent Advances and Future Prospects. [PDF]

Micromachines (Basel)
Moeinfard T, Ghafar-Zadeh E, Magierowski S.   +2 more
europepmc   +1 more source

Digitalized analog integrated circuits. [PDF]

Fundam Res
Zhu Z, Liu S.
europepmc   +1 more source

Some of the next articles are maybe not open access.

Related searches:

Design of power efficient All Digital Phase Locked Loop (ADPLL)

2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016
This paper presents a power efficient design of All Digital Phase Locked Loop (ADPLL). The proposed ADPLL uses power optimized digital loop filter instead of the conventional one. The power optimization of digital loop filter is carried out with the aid of clock gating technique without degrading the performance of the overall system.
Nitesh Tripathi, Sambhu Nath Pradhan
openaire   +3 more sources

A CMOS implementation of controller based all digital phase locked loop (ADPLL)

Circuit World, 2020
Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited
Vikas Balikai, Harish Kittur
openaire   +3 more sources

Design and simulation of FPGA based all digital phase locked loop (ADPLL)

2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT), 2017
Phase locked loops are most widely used in communication systems. Most of the PLL's that are used currently are hybrid type PLL's, where only the phase detectors are digital where as voltage controlled oscillators and loop filters are analog. This article presents an all digital approach for the design, simulation, Synthesis, and implementation of FPGA
Shruti Edway, R K Manjunath
openaire   +3 more sources

An all-digital phase-locked loop (ADPLL)-based clock recovery circuit

IEEE Journal of Solid-State Circuits, 1999
A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell.
Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee   +2 more
openaire   +3 more sources

All-Digital Phase Locked Loop (ADPLL) with an up-down counter using Simulink

2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2017
The concept of an All Digital Phase Locked Loop (ADPLL) with an up-down counter is conceived and presented here. The phase error of a Phase Detector (PD) in a Digital PLL is delivered in bits. The proposed structure enlists an Up-Down Counter to convert this phase error into a suitable input for the Digitally Controlled Oscillator (DCO).
V. Vaithianathan, V. H. Eshwar, S. Kamalakannan, James De Raja   +3 more
openaire   +3 more sources

All Digital Phase Locked Loop (ADPLL) and Its Blocks—A Comprehensive Knowledge

Smart Innovation, Systems and Technologies, 2022
Lalita Yadav, Manoj Duhan
openaire   +3 more sources

RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL)

2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO), 2022
Aaditya Joshi, Nishit Nathwani, Rutu Parekh   +2 more
openaire   +3 more sources