Results 31 to 40 of about 55,100,936 (115)

An Energy‐Efficient Ring Oscillator Based on Hybrid Voltage Gated Spin Orbit Torque/CMOS Circuit

Electronics Letters, Volume 61, Issue 1, January/December 2025.
This brief proposes a hybrid ring oscillator utilizing voltage gated spin orbit torque MTJ, achieves high power‐efficiency and low jitter performance. Solutions for ultra‐low power application contexts are provided. ABSTRACT Based on voltage gated spin orbit torque (VG‐SOT) MTJ and conventional CMOS circuits, a hybrid ring oscillator (RO) with high ...
Huai Yun, Weiwei Shi, Peng Chen, Xiaoying Deng   +3 more
wiley   +1 more source

RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity

, 2018
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li, Donald Y. C. Lie, Chaojiang Li, Dixian Zhao, Christian Fager   +4 more
wiley   +1 more source

Open‐Loop Wide‐Bandwidth Phase Modulation Techniques

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti, Kenichi Okada   +3 more
wiley   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators

Journal of Electrical and Computer Engineering, Volume 2025, Issue 1, 2025.
Time‐domain all‐digital‐phase‐locked‐loop phase‐shift‐keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low‐voltage nanoscale CMOS techology. Data‐bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators ...
Phanumas Khumsat, Thanabodee Koyphol, Tan Thongruk, Tidarat Inyod, Suman Lata Tripathi   +4 more
wiley   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

A Low‐Power Digitally Controlled Oscillator for All Digital Phase‐Locked Loops

VLSI Design, Volume 2010, Issue 1, 2010., 2010
A low‐power and low‐jitter 12‐bit CMOS digitally controlled oscillator (DCO) design is presented. The Low‐Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters.
Jun Zhao, Yong-Bin Kim, Gregory D. Peterson   +2 more
wiley   +1 more source

The Implementation and Analysis of an All-digital Phase-locked Loop [PDF]

, 2012
[[abstract]]An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time.
Chen, Po-Yueh; Su, Hung-Lung
core  

An Low-Jitter All-Digital Phased-Locked Loop Using a Suppresive Digital Loop Filter

, 2012
[[abstract]]In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1 ps resolution.
Hsuan-Jung Hsu;Shi-Yu Huang
core   +1 more source

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

IEEE Open Journal of the Solid-State Circuits Society
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski   +3 more
doaj   +1 more source