Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input [PDF]
, 2008 IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, USA, 18-21 May 2008Inherent to digital phase-locked loops is frequency quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference
Tertinek, Stefan +5 more
core +1 more source
A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices [PDF]
A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study.
Kihara, Takao +5 more
core +1 more source
System Level Modeling and Verification of All-digital Phase-locked Loop
, 2015 In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of ...
Zhang, Chi
core +2 more sources
An Effective Low Power Ring Oscillator Based All Digital Phase Locked Loop [PDF]
, 2019 The All digital phase-locked loops (ADPLL) widely employed in the data communication systems including, but not limited to, the implementation of the frequency multiplication and clock synchronization circuits.
Jeslin Jijo , J., R. Dinesh , Mr.
core
ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS
, 2011 The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ...
CHEN-FENG CHEN, YAWGENG A. CHAU
core +1 more source
Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]
Sensors (Basel), 2022 Lai WC.
europepmc +1 more source
A 5GHz 90-nm CMOS all digital phase-locked loop
, 2009 An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells.
Henrik Sjoland +3 more
core +1 more source
High-frequency Wide-Range All Digital Phase Locked Loop in 90nm CMOS [PDF]
, 2011 This thesis presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) in 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 2-7.2 GHz with wide linearity and high resolution.
Muppala, Prashanth
core +2 more sources
Frequency quantization in first-order digital phase-locked loops with frequency-modulated input [PDF]
, 2007 Presented at the International Workshop on Nonlinear Maps and their Applications (NOMA '07), INSA, Toulouse, December 13-14, 2007Frequency granularity in a digital phase-locked loop arises from quantization in the number-controlled oscillator which ...
Tertinek, Stefan +2 more
core +1 more source
Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]
Sensors (Basel), 2021 Sheng D, Chen WY, Huang HT, Tai L.
europepmc +1 more source