Results 51 to 60 of about 275 (117)
, 2004 Phase Locked Loops (PLLs) are widely used in clock recovery and frequency synthesis. Fully Digital PLLs are more suitable for the monolithic implementation with other circuits compared to the traditional implementations of the PLLs.
Gothandaraman, Akila
core
Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]
Sensors (Basel), 2022 Lai WC.
europepmc +1 more source
High Speed All Digital Phase-Locked Loop
, 2014 摘要 本篇論文描述一個高速全數位鎖相迴路的架構與設計，使用取樣編碼方式，能在四個參考週期內決定DCO操作模式及輸入信號在十六組頻率區段中的位置並局部修改演算流程與DCO設計，使本電路具有較快的搜尋速度、較短的鎖定時間、較小的Phase Jitter，並可操作在極高的頻率。架構中可分為數位控制振盪器，頻率偵測器、相位偵測器、UP/DN Counter、控制單元、啟動電路、取樣電路、編碼電路、位元指標器、除頻器及相位選擇器等十一個部分。操作程序可分為頻率獲取、相位獲取 ...
You, Rung-Hau, 游榮豪
core
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
, 2011 A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes ...
Abdulaziz, Mohammed +8 more
core +1 more source
Ultra-low phase noise ADPLL for millimeter wave
, 2020 Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption.
Zong, Zhirui, Staszewski, Robert Bogdan
core +1 more source
Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]
Sensors (Basel), 2021 Sheng D, Chen WY, Huang HT, Tai L.
europepmc +1 more source
ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS
, 2011 The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ...
CHEN-FENG CHEN, YAWGENG A. CHAU
core +1 more source
, 2020 This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self ...
Wei-Bin Yang; Hsi-Hua Wang; Hsin-I Chang; Yu-Lung Lo
core +1 more source
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
, 2012 [[abstract]]In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes.
Hsu, H.-J.;Huang, S.-Y.
core +1 more source
System Level Modeling and Verification of All-digital Phase-locked Loop
, 2015 In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of ...
Zhang, Chi
core