Results 51 to 60 of about 74 (65)
Some of the next articles are maybe not open access.
Modeling and Implementation of an All Digital Phase-Locked-Loop for Grid-Voltage Phase Detection
IEEE Transactions on Industrial Informatics, 2013Hua Geng
exaly
All-digital phase locked loop (ADPLL) system
2008VANSELOW FRANK, CHAN CHUNG SAN ROGER
openaire +1 more source
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Chia-Yu Yao
exaly
Automatic All-Digital Phase-Locked Loop System Design and optimization Tool
2020Hesham Omran, Khaled Sharaf
exaly
A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters
IEEE Transactions on Industrial Electronics, 2011Dewei Xu, Bin Wu, Hua Geng
exaly
A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO
IEEE Journal of Solid-State Circuits, 2010Shengdong Zhang
exaly
Digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit
2019YEO THENG TEE +4 more
openaire +4 more sources
An FPGA-Based Linear All-Digital Phase-Locked Loop
IEEE Transactions on Circuits and Systems I: Regular Papers, 2010Harald Klingbeil +2 more
exaly
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011exaly