Results 71 to 80 of about 275 (117)
High-frequency Wide-Range All Digital Phase Locked Loop in 90nm CMOS
, 2011 This thesis presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) in 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 2-7.2 GHz with wide linearity and high resolution.
Muppala, Prashanth
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A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider [PDF]
, 2009 A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang ...
Kim, Deok-Soo +4 more
core
Implementation of an All-digital Phase-locked Loop Using a New DCO
, 2012 [[abstract]]A novel digitally controlled oscillator (DCO) is implemented for All-digital phase lock loop (ADPLL) applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the ...
Chen, Po-Yueh; Su, Hung-Lung
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A fast phase tracking ADPLL for video pixel clock generation in 65 nm CMOS technology
, 2011 —A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC).
Ching-che Chung, Chiun-yao Ko
core +1 more source
Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop
, 2011 With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL.
Shen, Jue
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3.6/5.2GHz 듀얼 밴드를 갖는 All-Digital Fractional-N Phase-Locked Loop의 설계
, 2012 학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2012. 2. 정덕균.일반적으로 무선 통신 송수신 장치에는 주파수 합성기가 쓰인다. 주파수 합성기의 주요 구성회로의 하나인 위상동기화 루프 (PLL)는 무선 통신 규격을 만족시켜야 한다. 최근 이동통신 표준을 이끌고 있는 3GPP 연합의 LTE 규격의 경우 하위호환성을 만족하기 위해 매우 넓은 주파수영역을 만족해야하며 noise 특성 또한 매우 우수해야 한다.
임정필
core
, 2005 An all-digital phase locked loop (ADPLL) with cascaded dynamic phase average (DPA) loop for wide multiplication range applications is presented in this paper. The multiplication factor can range from 4 to 65025 (255 x 255).
Ching-che Chung +2 more
core
A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
, 2010 —A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented.
Heesoo Song +9 more
core +1 more source
A 2.4GHz All-Digital Adaptive-Locked Frequency Synthesizer
, 2014 最近幾十年來，在製程的進步和電晶體尺寸縮小的趨勢，這可使電路設計上得到更高的操作頻率和更少的功率消耗，卻不利於類比電路設計；反之，這種趨勢更有利於數位電路設計，因此已有許多的類比電路改以數位方式實現，如:鎖相迴路和資料時脈回復電路。本論文將分成四個部分來做介紹。 首先，第一部份則是探討一些基本的全數位鎖相迴路架構和其構成的單元。和通訊系統的應用頻帶與其規格。 第二部分則介紹目前三個種類的鎖相迴路，類比式的鎖相迴路，數位式的鎖相迴路以及全數位式的鎖相迴路。鎖相迴路的基本理論以及設計 ...
Huang, Ming-Yi, 黃名毅
core
Portable All-Digital Phase-Lock Loop Circuit Design With Programmable Pulse Width Control
, 2007 以鎖相迴路為基礎的時脈產生器，在時脈資料回復電路當中被廣泛的使用。振盪器決定鎖相迴路電路的操作頻率，為了符合更進階的應用，本論文提出一個適用於全數位式鎖相迴路的高速數位控制震盪器架構。提出的高速振盪器操作頻率介於140MHz至1040MHz，振盪器核心面積為345um*56um。此外，針對面積成本為考量的鎖相迴路應用，本論文也提出一個低成本的數位振盪器架構，讓控制單元複雜度大幅的降低。高速和彽成本的數位振盪器架構皆以UMC18 1P6M技術進行實作驗證，振盪器解析度皆可達到20ps ...
Wang, Wei, 汪威
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