Results 71 to 80 of about 55,100,936 (115)

Experimental Validation of Key Elemental Circuits for RSFQ All-Digital Phase Locked Loop

An all-digital phase-locked loop (ADPLL) is a critical component for generating a precise clock sequence synchronized to a reference signal. For applications in superconducting qubit control, RSFQ ADPLL technology is promising due to its high-speed ...
Yoshinao Mizugaki, Daiki Fukuyo
core   +1 more source

An All-Digital PLL with cascaded dynamic phase average loop for wide multiplication range applications

, 2005
An all-digital phase locked loop (ADPLL) with cascaded dynamic phase average (DPA) loop for wide multiplication range applications is presented in this paper. The multiplication factor can range from 4 to 65025 (255 x 255).
Ching-che Chung, Chen-yi Lee, Pao-lung Chen   +2 more
core  

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications [PDF]

, 2012
This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the ...
Dash, Suraj, Das, Abhishek
core  

A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix. [PDF]

Sensors (Basel), 2017
Zhang M, Wang H, Liu Y.
europepmc   +1 more source

Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype. [PDF]

Front Neurosci, 2018
Liu C, Bellec G, Vogginger B, Kappel D, Partzsch J, Neumärker F, Höppner S, Maass W, Furber SB, Legenstein R, Mayr CG.   +10 more
europepmc   +1 more source

A Review on Micro-Watts All-Digital Frequency Synthesizers. [PDF]

Micromachines (Basel)
Navaneethan V, Teo BCT, Muthukumaraswamy AA, Lim XY, Siek L.   +4 more
europepmc   +1 more source

3.6/5.2GHz 듀얼 밴드를 갖는 All-Digital Fractional-N Phase-Locked Loop의 설계

, 2012
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2012. 2. 정덕균.일반적으로 무선 통신 송수신 장치에는 주파수 합성기가 쓰인다. 주파수 합성기의 주요 구성회로의 하나인 위상동기화 루프 (PLL)는 무선 통신 규격을 만족시켜야 한다. 최근 이동통신 표준을 이끌고 있는 3GPP 연합의 LTE 규격의 경우 하위호환성을 만족하기 위해 매우 넓은 주파수영역을 만족해야하며 noise 특성 또한 매우 우수해야 한다.
임정필
core  

Research on ADPLL for High-Precision Phase Measurement

The inter-satellite laser interferometer, which functions as a high-performance displacement sensor, will be used in forthcoming space-based gravitational wave detection missions. The readout of these interferometers is typically performed by phasemeters
Chenying Sun, Xindong Liang, Jianjun Jia, Weilai Yao   +3 more
core   +1 more source

An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [PDF]

Sensors (Basel)
Nguyen TVH, Pham CK.
europepmc   +1 more source

Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology. [PDF]

Sci Rep
Modanlou S, Gholami M.
europepmc   +1 more source