A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix. [PDF]
Zhang M, Wang H, Liu Y.
europepmc +1 more source
Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype. [PDF]
Liu C +10 more
europepmc +1 more source
Modeling and Characterization of an All-Digital Phase-Locked Loop
The thesis "Modeling and Characterization of an All-Digital PLL" aims to create a behavioral model of an All-Digital Phase-Locked-Loop (ADPLL). The model should be able to perform accurate and time-effective simulations.
Johnson, Alfred, Andersson, Fredrik
core
A Review on Micro-Watts All-Digital Frequency Synthesizers. [PDF]
Navaneethan V +4 more
europepmc +1 more source
An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [PDF]
Nguyen TVH, Pham CK.
europepmc +1 more source
A new programmable low noise all digital phase-locked loop architecture
In the electronics industry today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC).
Gaither, Justin
core
Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology. [PDF]
Modanlou S, Gholami M.
europepmc +1 more source
A Low Voltage All-Digital Phase-Locked Loop Based on Differential Bootstrapped Ring Oscillator
自從1930年第一個鎖相迴路 (Phase-Locked Loop, PLL) 被提出之後,鎖相迴路已有著十分廣泛的應用,如當作數位系統的時脈產生器 (Clock Generator)、通訊系統中的本地振盪器 (Local Oscillator)、時脈及資料恢復電路 (Clock and Data Re- covery, CDR)…等等。以上應用皆需要十分精準的頻率及相位同步,以滿足規格要求。所以設計一個適當操作頻率及頻寬,並具有低相位抖動 (Jitter)、低相位雜訊 (Phase Noise ...
Wei, Chi-Hao, 魏啟豪
core
CMOS Point-of-Care Diagnostics Technologies: Recent Advances and Future Prospects. [PDF]
Moeinfard T +2 more
europepmc +1 more source
Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research
This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units.
Juan, Sung-lin
core

