Results 101 to 110 of about 275 (117)
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Single-Event Characterization of Bang-bang All-digital Phase-locked Loops (ADPLLs)
IEEE Transactions on Nuclear Science, 2015The single-event vulnerability of a bang-bang ADPLL is investigated through fault injection experiments and circuit simulations. Single-event upsets in the digital loop filter result in the worst-case error response of the ADPLL, often requiring phase reacquisition.
Y. P. Chen +7 more
openaire +1 more source
Design and Simulation of CMOS Fractional-N All-Digital Phase-Locked Loop (ADPLL)
2024 International Microwave and Antenna Symposium (IMAS)openaire +3 more sources
RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL)
2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO), 2022Aaditya Joshi +2 more
openaire +1 more source
Modeling and Implementation of an All Digital Phase-Locked-Loop for Grid-Voltage Phase Detection
IEEE Transactions on Industrial Informatics, 2013Hua Geng, Jianbo Sun
exaly
2025 IEEE International Microwave and Antenna Symposium (IMAS)
Mahmoud Desoky +2 more
openaire +1 more source
Mahmoud Desoky +2 more
openaire +1 more source
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Chia-Yu Yao
exaly
An FPGA-Based Linear All-Digital Phase-Locked Loop
IEEE Transactions on Circuits and Systems I: Regular Papers, 2010Martin Kumm +2 more
exaly
A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters
IEEE Transactions on Industrial Electronics, 2011Hua Geng, Dewei Xu, Bin Wu
exaly