Results 111 to 117 of about 275 (117)

Automatic All-Digital Phase-Locked Loop System Design and optimization Tool

2020
Hesham Omran, Khaled Sharaf
exaly  

Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

ETRI Journal, 2011
Younggun Pu, Kang-Yoon Lee
exaly  

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis

Lecture Notes in Computer Science, 2011
Oliver Schrape, Eckhard Grass
exaly  

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
exaly  

A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

IEEE Journal of Solid-State Circuits, 2010
exaly  

The Core Chip Design of Fast Locked All Digital Phase-locked Loop

2019
Yaqing Zhu
exaly  

A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

Kuo-Hsing Cheng
exaly