Results 61 to 70 of about 275 (117)
All-Digital Phase-Locked Loop for Radio Frequency Synthesis [PDF]
, 2014 It has been a constant challenge in wireless system design to meet the growing demand for an ever higher data rate and more diversified functionality at minimal cost and power consumption.
Xu, Liangge
core
, 2012 [[abstract]]In this paper we present a high-resolution and wide-range all-digital phase-locked loop (ADPLL), which is suitable to function as a clock generator.
Hsuan-Jung Hsu;Chun-Chieh Tu;Shi-Yu Huang
core +1 more source
The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop
, 2014 This paper is to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics
Chen, Kuang-Yuan; Chiang, Jen-Shiun
core
An analysis of ADPLL applications in various fields
, 2020 ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a
Dinesh, R. +3 more
core +1 more source
Wideband chirp generation techniques in digital phase-locked loops
, 2016 In this paper in-depth analysis and comparison of two popular FM techniques, namely, two-point modulation and pre-emphasis of the modulation signal are presented.
Roberto Nonis +7 more
core +1 more source
ALL Digital Phase-Locked Loop (ADPLL): A Survey
International Journal of Future Computer and Communication, 2013 Kusum Lata, Manoj Kumar
openaire +1 more source
Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing. [PDF]
Philos Trans A Math Phys Eng Sci, 2020 Miao L, Gao B, Li H, Tian G.
europepmc +1 more source
Design and implementation of ADPLL (All Digital Phase Lock Loop)
, 2018 Máster en Ingeniería de ...
openaire +1 more source
An Effective Low Power Ring Oscillator Based All Digital Phase Locked Loop
, 2019 The All digital phase-locked loops (ADPLL) widely employed in the data communication systems including, but not limited to, the implementation of the frequency multiplication and clock synchronization circuits.
Jeslin Jijo , J., R. Dinesh , Mr.
core
NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]
Sensors (Basel), 2020 Borejko T +11 more
europepmc +1 more source