Design and Implementation of an All Digital Phase Lock Loop
, 2007 In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits.
Tsai, Sheng-Chung, 蔡勝中
core
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
, 2011 A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes ...
Abdulaziz, Mohammed +12 more
core +1 more source
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
, 2011 [[abstract]]In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes.
Hsu, H.-J.;Huang, S.-Y. +2 more
core +1 more source
A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider [PDF]
, 2009 A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang ...
Kim, Deok-Soo +4 more
core
Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing. [PDF]
Philos Trans A Math Phys Eng Sci, 2020 Miao L, Gao B, Li H, Tian G.
europepmc +1 more source
ALL Digital Phase-Locked Loop (ADPLL): A Survey
International Journal of Future Computer and Communication, 2013 Kusum Lata, Manoj Kumar
openaire +1 more source
Wideband chirp generation techniques in digital phase-locked loops
, 2016 In this paper in-depth analysis and comparison of two popular FM techniques, namely, two-point modulation and pre-emphasis of the modulation signal are presented.
Roberto Nonis +7 more
core +1 more source
NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]
Sensors (Basel), 2020 Borejko T +11 more
europepmc +1 more source
A 5GHz 90-nm CMOS all digital phase-locked loop
, 2010 An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time.
Ping Lu +6 more
core +1 more source
The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop
, 2014 This paper is to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics
Chen, Kuang-Yuan; Chiang, Jen-Shiun
core +1 more source