Results 41 to 50 of about 132 (116)
IEEE AccessThis paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon +13 more
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A Robust and Efficient Fault-Resilient RadHard ADPLL
International Journal of Systems Applications, Engineering & Development, 2020 The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges.
Varsha Prasad, Sandya Prasad
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A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs
IEEE Access, 2023 This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time ...
Abdelrahman G. Habib +2 more
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A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL
IEEE Open Journal of the Solid-State Circuits SocietyThis article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang +9 more
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A High-Performance Time-to-Digital Converter in QCA Technology Employing a Low-Power D Flip-Flop
IEEE AccessThis paper presents a low-power and compact Time-to-Digital Converter (TDC) implemented using Quantum-dot Cellular Automata (QCA) technology. The proposed architecture extends our previous QCA-based TDC design by incorporating a multiplexer-based D-latch
Shahram Modanlou, Mohammad Gholami
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FPGA implementation of reconfigurable ADPLL network for distributed clock generation [PDF]
2011 International Conference on Field-Programmable Technology, 2011 This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described.
Shan, Chuan +9 more
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Guangtongxin yanjiu, 2006 文章首先介绍了全数字锁相环（ADPLL）的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟（SEC）设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列（FPGA）验证,给出了测试结果。
张继勇, 王爱国
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Digital Phase-Locked Loops: Exploring Different Boundaries
IEEE Open Journal of the Solid-State Circuits SocietyThis article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in
Yuncheng Zhang +2 more
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FPGA Implementation of ADPLL with Ripple Reduction Techniques
International Journal of VLSI Design & Communication Systems, 2012 In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation.
Manoj Kumar, Kusum Lata
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Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review
IEEE AccessThis paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a comprehensive categorization and in-depth analysis of their underlying working principles.
Debojyoti Dutta +3 more
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