Results 61 to 70 of about 133 (118)

A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix. [PDF]

Sensors (Basel), 2017
Zhang M, Wang H, Liu Y.
europepmc   +1 more source

Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype. [PDF]

Front Neurosci, 2018
Liu C, Bellec G, Vogginger B, Kappel D, Partzsch J, Neumärker F, Höppner S, Maass W, Furber SB, Legenstein R, Mayr CG.   +10 more
europepmc   +1 more source

An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [PDF]

Sensors (Basel)
Nguyen TVH, Pham CK.
europepmc   +1 more source

CMOS Point-of-Care Diagnostics Technologies: Recent Advances and Future Prospects. [PDF]

Micromachines (Basel)
Moeinfard T, Ghafar-Zadeh E, Magierowski S.   +2 more
europepmc   +1 more source

A critically co-endangered feather louse <i>Forficuloecus pezopori</i> n. sp. (Phthiraptera: Philopteridae) detected through conservation intervention for the western ground parrot <i>Pezoporus flaviventris</i> (Psittaculidae). [PDF]

Int J Parasitol Parasites Wildl
Martin SB, Keatley S, Wallace A, Vaughan-Higgins RJ, Ash A.   +4 more
europepmc   +1 more source

Digitalized analog integrated circuits. [PDF]

Fundam Res
Zhu Z, Liu S.
europepmc   +1 more source

A Time-Amplifier Gain Calibration Technique for ADPLL

A Time-Amplifier Gain Calibration Technique for ADPLL
identifier:oai:t2r2.star.titech.ac.jp ...
openaire   +1 more source

FPGA Based Modelling of an ADPLL Network [PDF]

2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019
This paper introduces and compares the implementation of a number of FPGA based ADPLL network prototyping architectures. Networks are then created using three different ADPLL implementations and tests performed on each. Based on these test results, comparison is made to both the expected performance and role of each ADPLL design as a development tool.
Elena Blokhina, D Galayko
exaly   +4 more sources

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FPGA Validation of Event-Driven ADPLL

2020 European Conference on Circuit Theory and Design (ECCTD), 2020
In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter.
Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina   +3 more
openaire   +1 more source

ADPLL design and implementation on FPGA

2013 International Conference on Intelligent Systems and Signal Processing (ISSP), 2013
This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 10.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper, implementation of ADPLL is described in detail.
Kusum Lata
exaly   +2 more sources