Results 61 to 70 of about 535 (152)
IEEE AccessThis paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon +13 more
doaj +1 more source
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices
, 2013 Ё In this paper, a 0.5V/1.0V low-power all-digital phase-locked loop (ADPLL) for battery-powered devices with a dynamic voltage and frequency scaling (DVFS) scheme is presented. The proposed frequency estimation algorithm with a fine-resolution monotonic
Ching-che Chung, Wei-siang Su, Duo Sheng
core +1 more source
A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications
, 2022 This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and the quantization
Shuilong Huang +5 more
core +1 more source
A clock network of distributed ADPLLs using an asymmetric comparison strategy [PDF]
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010 In this paper, we describe an architecture of a distributed ADPLL (All Digitall Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve ...
Korniienko, A. +5 more
openaire +2 more sources
, 2010 In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to ...
鄭國興; Cheng, Kuo-hsing; Chen, Yu-jung
core +1 more source
Ultra-low phase noise ADPLL for millimeter wave
, 2020 Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption.
Zong, Zhirui, Staszewski, Robert Bogdan
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A High-Performance Time-to-Digital Converter in QCA Technology Employing a Low-Power D Flip-Flop
IEEE AccessThis paper presents a low-power and compact Time-to-Digital Converter (TDC) implemented using Quantum-dot Cellular Automata (QCA) technology. The proposed architecture extends our previous QCA-based TDC design by incorporating a multiplexer-based D-latch
Shahram Modanlou, Mohammad Gholami
doaj +1 more source
Conception portable d'une ADPLL pour des applications TV
, 2009 Dans un systeme radio communication pour les applications hautes frequences (>300 mhz), la partie frontal RF est généralement analogique et alors moins compatible avec la partie numérique bande de base. La consommation d énergie, la surface et le coût de
RIFFAUD-DESGREYS, Patricia +1 more
core +2 more sources
, 2011 The frequency synthesizer, which functions as a local oscillator, is a critical block in the transceiver. It needs to meet very stringent specifications and consume as less power as possible.
Jiang, W. (author)
core
, 2022 5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum.
Zhang, Xiaomeng
core