Results 81 to 90 of about 535 (152)
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking
, 2012 International audienceAn architecture of All-Digital Phase-Locked Loop (ADPLL) with sliding window for wide range frequency tracking is proposed to reduce energy consumption and to accelerate convergence.
Anceau, François +5 more
core +1 more source
, 2019 A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally controlled oscillator (DCO) with split transformer and dual-path exponentially ...
Luong, Howard C., Huang, Zhiqiang
core +1 more source
DTC and TDC IC Design for Ultra-Low-Power ADPLL
, 2014 The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the main two power consuming blocks. Modifying the phase detection part based on phase
Chen, P. (author)
core
, 2022 An All-Digital Phase-Locked Loop (ADPLL) is an architecture that is widely employed in the communication system due to the advancement of the Complementary Metal-Oxide-Semiconductor (CMOS) technology process.
Nayan, Nazrul Anuar +3 more
core
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications
, 2008 —In this paper, we propose a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel 2-level flash timeto-digital converter (TDC) to
core
, 2015 This paper presents a single-chip digital-intensive polar transmitter for WCDMA and WLAN integrating a low-phase-noise all-digital phase-locked loop (ADPLL), a digitally-controlled wideband phase/amplitude modulator, and a calibration-free high-linearity
Luong, Howard C., Zheng, Shiyuan
core +1 more source
A 4μW, ADPLL-based implantable amperometric biosensor in 65nm CMOS
, 2017 This paper presents a fully implantable, wirelessly powered subcutaneous amperometric biosensor. We propose a novel ultra-low power all-digital phase-locked loop (ADPLL) based potentiostat architecture for electrochemical sensing.
Manuel Monge +13 more
core +1 more source
NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]
Sensors (Basel), 2020 Borejko T +11 more
europepmc +1 more source
, 2014 This thesis deals with the design of a duty-cycled, fractional-N and low-noise Phase Locked Loop (PLL) used for Ultra-Wideband applications in 40 nm process. This is the first-ever Duty-Cycled PLL (DCPLL) that is designed with an LC oscillator and brings
Gao, Y. (author)
core
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
, 2018 This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any ...
Ju, H +7 more
core +1 more source