Results 81 to 90 of about 132 (116)

A Framework for Automatic Generation of Fully Synthesizable ADPLL

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018
We propose a framework that can generate all digital PLL (ADPLL) from the design specifications. It uses double loop edge injection type ADPLL[1] with phase interpolation oscillator. A calibration logic to correct errors of two oscillators is introduced based on [1].
Shinya Ubukata, Satoshi Komatsu
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A glitch-corrector circuit for low-spur ADPLLs

Analog Integrated Circuits and Signal Processing, 2011
This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an All-Digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts.
ZANUSO, MARCO, LEVANTINO, SALVATORE, SAMORI, CARLO, LACAITA, ANDREA LEONARDO   +3 more
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Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008
Event driven phase noise simulation and modeling of an ADPLL by SystemVerilog is presented in this paper. It uses the simple Stochastic Voss-McCartney algorithm to generate the pink noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared to the circuit level simulation, it allows ...
Tingjun Wen, Tadeusz Kwasniewski
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A fractional frequency synthesizer based on ADPLL

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2004
In this paper, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A new phase frequency acquisition mode is involved with an initial half-step size to speed up the convergence in phase and frequency comparisons.
null Chia-Chun Tsai, null Hsu-Heng Wu, null Wen-Ta Lee   +2 more
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Ultra-low-power ADPLL

2020
To realize ULP fractional-N ADPLL with low jitter and low spurs, the first-order DSM-based fractional controller works in conjunction with a highly linear DTC. The rms jitter can be improved when compared to using higher-order DSM, and for this a DTC with high linearity is required.
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A Digitally Controlled Oscillator for ADPLL Application

Applied Mechanics and Materials, 2012
In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication.
Xiu Long Wu, Fa Niu Wang, Zhi Ting Lin, Jun Ning Chen   +3 more
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An asynchronous delay line TDC for ADPLL in 0.13um CMOS

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
This paper presents an asynchronous coarse-fine delay line based time to digital converter (TDC) applied to ADPLL. We develop asynchronous coarse-fine delay line architecture to balance measurement and resolution with lower power consumption. Auto control module is developed for switching between coarse and fine line. Phase detectable range is expanded
Chunhui Li, Lei Ma, Junhui Xiang, Hao Min   +3 more
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A high-speed variable phase accumulator for an ADPLL architecture

2008 IEEE International Symposium on Circuits and Systems, 2008
This paper presents a high-speed topology for the variable phase accumulator (VPA) in an all digital phase-locked loop (ADPLL) architecture. The topology increases the speed of the VPA, which is a digital block running at the highest frequency in the ADPLL. The high-speed feature of the topology is achieved by exploiting the fact that the VPA output is
Liangge Xu, Saska Lindfors
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Analytical Predictions of Phase Noise in ADPLLs

2013
In this chapter, we will derive analytical predictions of the phase noise in TDC-based and accumulator-based ADPLLs with \(l\)th-order noise shaping TDCs and DCO driven by a sigma-delta modulator.
Francesco Brandonisio, Michael Peter Kennedy   +1 more
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A mixed mode design flow for multi GHz ADPLLs

2011 NORCHIP, 2011
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved
Muhammad Shakir, Mohammed Abdulaziz, Ping Lu 0002, Pietro Andreani   +3 more
openaire   +1 more source