Results 81 to 90 of about 133 (118)

A high-speed variable phase accumulator for an ADPLL architecture

2008 IEEE International Symposium on Circuits and Systems, 2008
This paper presents a high-speed topology for the variable phase accumulator (VPA) in an all digital phase-locked loop (ADPLL) architecture. The topology increases the speed of the VPA, which is a digital block running at the highest frequency in the ADPLL. The high-speed feature of the topology is achieved by exploiting the fact that the VPA output is
Liangge Xu, Saska Lindfors
openaire   +2 more sources

ADPLL design parameters determinations through noise modeling

The Integration VLSI Journal, 2015
This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur.
Bo Jiang, Tian Xia
exaly   +2 more sources

Analytical Predictions of Phase Noise in ADPLLs

2013
In this chapter, we will derive analytical predictions of the phase noise in TDC-based and accumulator-based ADPLLs with \(l\)th-order noise shaping TDCs and DCO driven by a sigma-delta modulator.
Francesco Brandonisio, Michael Peter Kennedy   +1 more
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An asynchronous delay line TDC for ADPLL in 0.13um CMOS

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
This paper presents an asynchronous coarse-fine delay line based time to digital converter (TDC) applied to ADPLL. We develop asynchronous coarse-fine delay line architecture to balance measurement and resolution with lower power consumption. Auto control module is developed for switching between coarse and fine line. Phase detectable range is expanded
Chunhui Li, Lei Ma, Junhui Xiang, Hao Min   +3 more
openaire   +2 more sources

A novel ADPLL design using successive approximation frequency control

Microelectronics Journal, 2009
This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter.
Holger Eisenreich, Christian Mayr 0001, Stephan Henker, Michael Wickert, René Schüffny   +4 more
exaly   +3 more sources

A Fast-Locking ADPLL with Time Measurable DCO

Advanced Materials Research, 2012
This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle.
Tae Ho Lim, Ki Jin Kim, S. H. Park, K. H. Ahn   +3 more
openaire   +1 more source

A mixed mode design flow for multi GHz ADPLLs

2011 NORCHIP, 2011
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved
Muhammad Shakir, Mohammed Abdulaziz, Ping Lu 0002, Pietro Andreani   +3 more
openaire   +2 more sources

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

2009 IEEE International Symposium on Circuits and Systems, 2009
A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan, Debapriya Sahu, Khurram Waheed, John L. Wallberg, Robert Bogdan Staszewski   +8 more
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A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
A low power time-to-digital converter (TDC) with high resolution is presented in this paper. The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a phase-prediction technique. A snapshot circuit is used to reduce the sampling rate from digitally-controlled oscillator (DCO) frequency to reference frequency, thus greatly
Xusong Liu, Lei Ma, Junhui Xiang, Na Yan, Haolv Xie, Xiaowei Cai   +5 more
openaire   +1 more source

Comparison of Two ADPLL Structures for IoT Applications

2019 International Conference on Recent Advances in Energy-efficient Computing and Communication (ICRAECC), 2019
All digital Phase locked loop (ADPLL) based wireless transceiver is a key block in IoT based wireless communications. Locking time, power consumption and frequency resolution of ADPLL are the most important parameters to be considered in increasing the efficiency of IoT applications.
R. Dinesh, Ramalatha Marimuthu
exaly   +2 more sources