Results 91 to 100 of about 133 (118)
Some of the next articles are maybe not open access.
The FPGA implement of ADPLL without retimed clock
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, 2011A modified method to evaluate the phase of all digital phase-locked loop (ADPLL) output signal is proposed in this paper for improving the robustness property of the loop. The reference clock is used throughout the system as the synchronous clock, which can avoid the metastable output and the injection spurs caused by retiming mechanism, and ...
null Shuai Jiang +2 more
openaire +1 more source
A Contribution to the Discrete Z-Domain Analysis of ADPLL
2007 7th International Conference on ASIC, 2007In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the
null Xin Chen +2 more
openaire +1 more source
Synthesizable ADPLL Generator: From Specification to GDS
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023Kyumin Kwon, David D. Wentzloff
openaire +1 more source
Efficient Modeling and Simulation of Accumulator-Based ADPLLs
2013In this chapter, we focus on the behavioral modeling and simulation of accumulator-based ADPLLs. First, we introduce some basic concepts related to mixed-signal systems and simulators. We highlight the major issues for the simulation of an ADPLL as an example mixed-signal system.
Francesco Brandonisio +1 more
openaire +1 more source
An ADPLL Design Model Based on LoRa IoT Application
2023 IEEE 15th International Conference on ASIC (ASICON), 2023Yiyun Mao +4 more
openaire +1 more source
FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL
Lecture Notes in Electrical Engineering, 2023Huirem Bharat Meitei
exaly