Results 91 to 100 of about 132 (116)

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

2009 IEEE International Symposium on Circuits and Systems, 2009
A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan, Debapriya Sahu, Khurram Waheed, John L. Wallberg, Robert Bogdan Staszewski   +8 more
openaire   +1 more source

Synthesizable ADPLL Generator: From Specification to GDS

2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023
Kyumin Kwon, David D. Wentzloff
openaire   +1 more source

Efficient Modeling and Simulation of Accumulator-Based ADPLLs

2013
In this chapter, we focus on the behavioral modeling and simulation of accumulator-based ADPLLs. First, we introduce some basic concepts related to mixed-signal systems and simulators. We highlight the major issues for the simulation of an ADPLL as an example mixed-signal system.
Francesco Brandonisio, Michael Peter Kennedy   +1 more
openaire   +1 more source

An ADPLL Design Model Based on LoRa IoT Application

2023 IEEE 15th International Conference on ASIC (ASICON), 2023
Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu 0005, Na Yan 0004   +4 more
openaire   +1 more source

Research Valorization: Radiation-Hardened ADPLL

2023
Arijit Karmakar, Valentijn De Smedt, Paul Leroux   +2 more
openaire   +1 more source

All Digital Phase Locked Loop (ADPLL) and Its Blocks—A Comprehensive Knowledge

Smart Innovation, Systems and Technologies, 2022
Manoj Duhan
exaly  

FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL

Lecture Notes in Electrical Engineering, 2023
Huirem Bharat Meitei
exaly  

A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications

Electronics (Switzerland), 2022
Xiaosong Wang, Qinan Chen, Shuilong Huang   +2 more
exaly  

Design for test of a mm-Wave ADPLL-based transmitter

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Wanghua Wu, Robert Bogdan Staszewski, John R. Long   +2 more
openaire   +1 more source

Design for Test of the mm-Wave ADPLL

2016
Wanghua Wu, Robert Bogdan Staszewski, John R. Long   +2 more
openaire   +1 more source