Results 111 to 118 of about 133 (118)

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

IEEE Journal of Solid-State Circuits, 2010
Enrico Stefano Temporiti Milani, Colin Weltin-Wu, Daniele Baldi   +2 more
exaly  

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
Shi-Yu Huang
exaly  

ADPLL

2013
openaire   +2 more sources

Design and implementation of ADPLL for Digital communication applications

2017
Manoj Kumar
exaly  

A noval fast-locking ADPLL based on Newton's Method

2018
Xiaoying Deng, Mingcheng Zhu
exaly  

ADPLL FREQUENCY SYNTHESIZER

2009
openaire   +1 more source

ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE

2011
ENDO RYO, SHIMBO JIRO, KITAMURA TOMOMITSU   +2 more
openaire   +2 more sources

ADPLL with a TDC having a reduced DTC range

2016
openaire   +1 more source