Results 111 to 120 of about 535 (152)
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ADPLL design parameters determinations through noise modeling
The Integration VLSI Journal, 2015This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur.
Tian Xia
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Comparison of Two ADPLL Structures for IoT Applications
2019 International Conference on Recent Advances in Energy-efficient Computing and Communication (ICRAECC), 2019All digital Phase locked loop (ADPLL) based wireless transceiver is a key block in IoT based wireless communications. Locking time, power consumption and frequency resolution of ADPLL are the most important parameters to be considered in increasing the efficiency of IoT applications.
R Dinesh
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A novel ADPLL design using successive approximation frequency control
Microelectronics Journal, 2009This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter.
R Schüffny
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Design and implementation of ADPLL for Digital communication applications
2017 2nd International Conference for Convergence in Technology (I2CT), 2017ADPLL has a great role in Digital Communication. This paper presents the design and implementation of ADPLL for digital communication applications. All the blocks of ADPLL are designed as digital. The center frequency of the ADPLL is 200 kHz. The lock range of ADPLL is from 188 kHz to 212 kHz.
Manoj Kumar
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IEEE Journal of Solid-State Circuits, 2022 This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC).
Hyojun Kim, Woosong Jung, Sungwoo Kim
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FPGA Validation of Event-Driven ADPLL
2020 European Conference on Circuit Theory and Design (ECCTD), 2020In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter.
Eugene Koskin +3 more
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A Broadband ADPLL Design with Automatic Mode Change
2022 7th International Conference on Integrated Circuits and Microsystems (ICICM), 2022Zhen Shen, Xin-Hao Xu, Cheng Liu
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A glitch-corrector circuit for low-spur ADPLLs
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an All-Digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts. This technique is applied to the design of a 90-nm CMOS ADPLL
ZANUSO, MARCO +5 more
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A Low Jitter ADPLL for Mobile Applications
IEICE Transactions on Electronics, 2005This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type.
Kwang-Jin Lee +4 more
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IEEE Journal of Solid-State Circuits, 2010 Nonlinearities in the time-to-digital converter (TDC) are a significant source of fractional spurs in a divider-less fractional-N ADPLL. Using an abstract model for the TDC, this paper presents a dithering method which is mathematically shown to suppress
Enrico Temporiti +2 more
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