Results 131 to 140 of about 535 (152)

Analytical Predictions of Phase Noise in ADPLLs

2013
In this chapter, we will derive analytical predictions of the phase noise in TDC-based and accumulator-based ADPLLs with \(l\)th-order noise shaping TDCs and DCO driven by a sigma-delta modulator.
Francesco Brandonisio, Michael Peter Kennedy   +1 more
openaire   +1 more source

A mixed mode design flow for multi GHz ADPLLs

2011 NORCHIP, 2011
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved
Muhammad Shakir, Mohammed Abdulaziz, Ping Lu 0002, Pietro Andreani   +3 more
openaire   +1 more source

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

2009 IEEE International Symposium on Circuits and Systems, 2009
A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan, Debapriya Sahu, Khurram Waheed, John L. Wallberg, Robert Bogdan Staszewski   +8 more
openaire   +1 more source

A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
A low power time-to-digital converter (TDC) with high resolution is presented in this paper. The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a phase-prediction technique. A snapshot circuit is used to reduce the sampling rate from digitally-controlled oscillator (DCO) frequency to reference frequency, thus greatly
Xusong Liu, Lei Ma, Junhui Xiang, Na Yan, Haolv Xie, Xiaowei Cai   +5 more
openaire   +1 more source

Design of ADPLL system for WiMAX applications in 40-nm CMOS

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012
We present an all-digital phase-locked loop (ADPLL)-based frequency synthesizer for WiMAX applications implemented in 40-nm CMOS. Via frequency planning and design of multiple capacitor-banks in a digitally-controlled oscillator (DCO), the ADPLL covers dual bands of 2.3-2.7 GHz and 3.3-3.8 GHz, while achieving a fine frequency resolution of 25 Hz.
Wenlong Jiang, Armin Tavakol, Popong Effendrik, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski   +5 more
openaire   +1 more source

The FPGA implement of ADPLL without retimed clock

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, 2011
A modified method to evaluate the phase of all digital phase-locked loop (ADPLL) output signal is proposed in this paper for improving the robustness property of the loop. The reference clock is used throughout the system as the synchronous clock, which can avoid the metastable output and the injection spurs caused by retiming mechanism, and ...
null Shuai Jiang, null Songbai He, null Fei You   +2 more
openaire   +1 more source

A Contribution to the Discrete Z-Domain Analysis of ADPLL

2007 7th International Conference on ASIC, 2007
In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the
null Xin Chen, null Jun Yang, null Xiao-ying Deng   +2 more
openaire   +1 more source

Efficient Modeling and Simulation of Accumulator-Based ADPLLs

2013
In this chapter, we focus on the behavioral modeling and simulation of accumulator-based ADPLLs. First, we introduce some basic concepts related to mixed-signal systems and simulators. We highlight the major issues for the simulation of an ADPLL as an example mixed-signal system.
Francesco Brandonisio, Michael Peter Kennedy   +1 more
openaire   +1 more source

Synthesizable ADPLL Generator: From Specification to GDS

2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023
Kyumin Kwon, David D. Wentzloff
openaire   +1 more source

An ADPLL Design Model Based on LoRa IoT Application

2023 IEEE 15th International Conference on ASIC (ASICON), 2023
Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu 0005, Na Yan 0004   +4 more
openaire   +1 more source