Results 141 to 150 of about 535 (152)
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Design for test of a mm-Wave ADPLL-based transmitter
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Wanghua Wu +2 more
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FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL
Lecture Notes in Electrical Engineering, 2023Huirem Bharat Meitei
exaly
A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010Wen-Chung Shen, An-Yeu Wu
exaly
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Ching-Che Chung
exaly
A low-power ADPLL using feedback DCO quarterly disabled in time domain
Microelectronics Journal, 2008Chua-Chin Wang
exaly
Design of ADPLL for both large lock-in range and good tracking performance
IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 1999In-Joong Ha
exaly
Contributions to the analysis of deterministic noise on ADPLL jitter performance
Analog Integrated Circuits and Signal Processing, 2011Xiaoying Deng, Jianhui Wu
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