Results 121 to 130 of about 535 (152)

An ADPLL circuit using a DDPS for genlock applications

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12 MHz and 200 MHz, with a frequency between 24 Hz and 100 MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator.
Dorin Emil Calbaza, Ioan Cordos, Nigel Seth-Smith, Yvon Savaria   +3 more
openaire   +1 more source

A Framework for Automatic Generation of Fully Synthesizable ADPLL

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018
We propose a framework that can generate all digital PLL (ADPLL) from the design specifications. It uses double loop edge injection type ADPLL[1] with phase interpolation oscillator. A calibration logic to correct errors of two oscillators is introduced based on [1].
Shinya Ubukata, Satoshi Komatsu
openaire   +1 more source

Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008
Event driven phase noise simulation and modeling of an ADPLL by SystemVerilog is presented in this paper. It uses the simple Stochastic Voss-McCartney algorithm to generate the pink noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared to the circuit level simulation, it allows ...
Tingjun Wen, Tadeusz Kwasniewski
openaire   +1 more source

A glitch-corrector circuit for low-spur ADPLLs

Analog Integrated Circuits and Signal Processing, 2011
This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an All-Digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts.
ZANUSO, MARCO, LEVANTINO, SALVATORE, SAMORI, CARLO, LACAITA, ANDREA LEONARDO   +3 more
openaire   +1 more source

A fractional frequency synthesizer based on ADPLL

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2004
In this paper, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A new phase frequency acquisition mode is involved with an initial half-step size to speed up the convergence in phase and frequency comparisons.
null Chia-Chun Tsai, null Hsu-Heng Wu, null Wen-Ta Lee   +2 more
openaire   +1 more source

A Digitally Controlled Oscillator for ADPLL Application

Applied Mechanics and Materials, 2012
In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication.
Xiu Long Wu, Fa Niu Wang, Zhi Ting Lin, Jun Ning Chen   +3 more
openaire   +1 more source

A high-speed variable phase accumulator for an ADPLL architecture

2008 IEEE International Symposium on Circuits and Systems, 2008
This paper presents a high-speed topology for the variable phase accumulator (VPA) in an all digital phase-locked loop (ADPLL) architecture. The topology increases the speed of the VPA, which is a digital block running at the highest frequency in the ADPLL. The high-speed feature of the topology is achieved by exploiting the fact that the VPA output is
Liangge Xu, Saska Lindfors
openaire   +1 more source

An asynchronous delay line TDC for ADPLL in 0.13um CMOS

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
This paper presents an asynchronous coarse-fine delay line based time to digital converter (TDC) applied to ADPLL. We develop asynchronous coarse-fine delay line architecture to balance measurement and resolution with lower power consumption. Auto control module is developed for switching between coarse and fine line. Phase detectable range is expanded
Chunhui Li, Lei Ma, Junhui Xiang, Hao Min   +3 more
openaire   +1 more source

Ultra-low-power ADPLL

2020
To realize ULP fractional-N ADPLL with low jitter and low spurs, the first-order DSM-based fractional controller works in conjunction with a highly linear DTC. The rms jitter can be improved when compared to using higher-order DSM, and for this a DTC with high linearity is required.
openaire   +1 more source

A Fast-Locking ADPLL with Time Measurable DCO

Advanced Materials Research, 2012
This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle.
Tae Ho Lim, Ki Jin Kim, S. H. Park, K. H. Ahn   +3 more
openaire   +1 more source