Results 101 to 110 of about 133 (118)
Some of the next articles are maybe not open access.
Design for test of a mm-Wave ADPLL-based transmitter
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Wanghua Wu +2 more
openaire +1 more source
A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010Wen-Chung Shen, An-Yeu Wu
exaly
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Ching-Che Chung, Chi-Kuang Lo
exaly
A low-power ADPLL using feedback DCO quarterly disabled in time domain
Microelectronics Journal, 2008Chua-Chin Wang +2 more
exaly
Method of improving noise characteristics of an ADPLL and a relative ADPLL
2010WELTIN-WU COLIN +2 more
openaire +2 more sources
Design of ADPLL for both large lock-in range and good tracking performance
IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 1999In-Joong Ha
exaly
A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology
Analog Integrated Circuits and Signal Processing, 2013Yu Wang, Bo Zhao, Yong Lian
exaly
Fractional-N ADPLL with reference dithering
2023MOEHLMANN ULRICH, MISSELWITZ KAI HENDRIK
openaire +1 more source
Contributions to the analysis of deterministic noise on ADPLL jitter performance
Analog Integrated Circuits and Signal Processing, 2011Jianhui Wu
exaly