Results 101 to 110 of about 535 (152)
The Implementation and Analysis of an All-digital Phase-locked Loop
, 2012 [[abstract]]An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time.
Chen, Po-Yueh; Su, Hung-Lung
core
A CMOS digital polar transmitter with low noise ADPLL and high linear PA
, 2013 Digitally-intensive RF design has attracted a lot of attention recently because it is highly programmable for multi-standard operation and enables high system integration with digital baseband and application processors on the same die. Moreover, many RF
Zheng, Shiyuan
core
A critically co-endangered feather louse <i>Forficuloecus pezopori</i> n. sp. (Phthiraptera: Philopteridae) detected through conservation intervention for the western ground parrot <i>Pezoporus flaviventris</i> (Psittaculidae). [PDF]
Int J Parasitol Parasites WildlMartin SB +4 more
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Fast locking time을 갖는 All-Digital PLL에 대한 성능 분석과 평가
, 2010 학위논문(석사) - 한국과학기술원 : 정보통신공학과, 2010.2, [ vii, 62 p. ]In this thesis, we evaluate and analyze of the All-Digital Phase Locked Loop (ADPLL). We mention about metastability problems from the retiming logic and time-to-digital converter (TDC) in the ADPLL,
김응룡, Kim, Eung-Ryoung
core
Comparison of various optimized architectures of DCO for ADPLL
Contemporary Engineering Sciences, 2014 B. Narendran, R. Parameshwaran
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A Time-Amplifier Gain Calibration Technique for ADPLL
A Time-Amplifier Gain Calibration Technique for ADPLLidentifier:oai:t2r2.star.titech.ac.jp ...
openaire
DESIGN AND SIMULATION OF DIGITALLY CONTROLLED OSCILLATOR OF ADPLL
International Journal of Advanced Scientific Technologies in Engineering and Management Sciences, 2019 C. Divya +3 more
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Built-In Speed Grading with a Process-Tolerant ADPLL
16th Asian Test Symposium (ATS 2007), 2007 Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry.
Hsuan-Jung Hsu +2 more
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ADPLL design and implementation on FPGA
2013 International Conference on Intelligent Systems and Signal Processing (ISSP), 2013This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 10.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper, implementation of ADPLL is described in detail.
Kusum Lata
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