Results 101 to 110 of about 132 (116)

Clock synchronization in an ADPLL

2020
PAVLOVIC NENAD, DYACHENKO VLADISLAV
openaire   +1 more source

A low-power ADPLL using feedback DCO quarterly disabled in time domain

Microelectronics Journal, 2008
Chua-Chin Wang
exaly  

Design of ADPLL for both large lock-in range and good tracking performance

IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 1999
In-Joong Ha
exaly  

Detailed Study on a Robust and Efficient Fault-Resilient Rad Hard ADPLL

2021
exaly  

Method of improving noise characteristics of an ADPLL and a relative ADPLL

2010
WELTIN-WU COLIN, TEMPORITI MILANI ENRICO STEFANO, BALDI DANIELE   +2 more
openaire   +2 more sources

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Ching-Che Chung
exaly  

Design and implementation of a low-area reconfigurable and synthesizable digital loop filter for ADPLL

2023
Kang-Yoon Lee, Nabeel Ahmad
exaly  

Fractional-N ADPLL with reference dithering

2023
MOEHLMANN ULRICH, MISSELWITZ KAI HENDRIK
openaire   +1 more source

An 11-bit and 39 ps resolution time-to-digital converter for ADPLL in digital television

International Journal of Electronics, 2010
Shengdong Zhang
exaly  

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

IEEE Journal of Solid-State Circuits, 2010
Enrico Stefano Temporiti Milani, Colin Weltin-Wu, Daniele Baldi   +2 more
exaly