Results 71 to 80 of about 132 (116)
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ADPLL design and implementation on FPGA
2013 International Conference on Intelligent Systems and Signal Processing (ISSP), 2013This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 10.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper, implementation of ADPLL is described in detail.
Kusum Lata
exaly +2 more sources
ADPLL design parameters determinations through noise modeling
The Integration VLSI Journal, 2015This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur.
Bo Jiang, Tian Xia
exaly +2 more sources
Comparison of Two ADPLL Structures for IoT Applications
2019 International Conference on Recent Advances in Energy-efficient Computing and Communication (ICRAECC), 2019All digital Phase locked loop (ADPLL) based wireless transceiver is a key block in IoT based wireless communications. Locking time, power consumption and frequency resolution of ADPLL are the most important parameters to be considered in increasing the efficiency of IoT applications.
R. Dinesh, Ramalatha Marimuthu
exaly +2 more sources
A novel ADPLL design using successive approximation frequency control
Microelectronics Journal, 2009This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter.
Holger Eisenreich +4 more
exaly +2 more sources
A Fast-Locking ADPLL with Time Measurable DCO
Advanced Materials Research, 2012This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle.
K H Ahn
exaly +2 more sources
FPGA Validation of Event-Driven ADPLL
2020 European Conference on Circuit Theory and Design (ECCTD), 2020In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter.
Eugene Koskin +3 more
openaire +1 more source
A glitch-corrector circuit for low-spur ADPLLs
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an All-Digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts. This technique is applied to the design of a 90-nm CMOS ADPLL
ZANUSO, MARCO +5 more
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A Low Jitter ADPLL for Mobile Applications
IEICE Transactions on Electronics, 2005This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type.
Kwang-Jin Lee +4 more
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An ADPLL circuit using a DDPS for genlock applications
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12 MHz and 200 MHz, with a frequency between 24 Hz and 100 MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator.
Dorin Emil Calbaza +3 more
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Built-In Speed Grading with a Process-Tolerant ADPLL
16th Asian Test Symposium (ATS 2007), 2007Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry.
Hsuan-Jung Hsu +2 more
openaire +1 more source