Results 71 to 80 of about 535 (152)
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS
, 2021 In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS.
Yuan, Min Shueh +17 more
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A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
, 2012 [[abstract]]In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes.
Hsu, H.-J.;Huang, S.-Y.
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A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL
, 2013 A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required.
Te Han +5 more
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An Ultra-Low-Power ADPLL for WPAN Applications
, 2013 RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios. Compared to analog PLLs, all-digital phase-locked loops (ADPLLs) are preferred in nanoscale CMOS,
Chillara, V.K. (author)
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, 2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ...
Liu, Yao-Hong +4 more
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A fast phase tracking ADPLL for video pixel clock generation in 65 nm CMOS technology
, 2011 —A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC).
Ching-che Chung, Chiun-yao Ko
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All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator
, 2011 A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA.
Rong, Liang, +7 more
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Phase noise improvement and noise modeling of type-I ADPLL with non-linear quantization effects
, 2014 This paper presents a phase noise improvement method for fine tuning of type-I ADPLL by exploiting its nonlinear quantization effects. When quantization step approaches the same orders of magnitude of standard deviation of input noise, quantization ...
Zheng, Lirong +14 more
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Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS
, 2011 WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access.
Effendrik, P. (author)
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An Ultra-Low-Power ADPLL for BLE Applications
, 2014 In recent years, wireless personal area network (WPAN) applications have triggered the needs for low-cost and low-power PLLs which also provide good performance.
Wu, L. (author)
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