Results 51 to 60 of about 133 (118)

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

IEEE Open Journal of the Solid-State Circuits Society
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski   +2 more
doaj   +1 more source

Linearity Calibration Method for Stochastic Time-to-Digital Converters

IEEE Access
Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj   +1 more source

FPGA Implementation of ADPLL with Ripple Reduction Techniques

International Journal of VLSI Design & Communication Systems, 2012
In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation.
Manoj Kumar, Kusum Lata
openaire   +1 more source

Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]

Sensors (Basel), 2021
Sheng D, Chen WY, Huang HT, Tai L.
europepmc   +1 more source

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]

Sensors (Basel), 2022
Lai WC.
europepmc   +1 more source

Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing. [PDF]

Philos Trans A Math Phys Eng Sci, 2020
Miao L, Gao B, Li H, Tian G.
europepmc   +1 more source

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]

Sensors (Basel), 2020
Borejko T, Marcinek K, Siwiec K, Narczyk P, Borkowski A, Butryn I, Łuczyk A, Pietroń D, Plasota M, Reszewicz S, Wiechowski Ł, Pleskacz WA.   +11 more
europepmc   +1 more source

Design of a digitally controlled ring oscillator for ADPLL

, 2022
Sayısal olarak kontrol edilen osilatör, özellikle PLL'lerde geniş kullanımları nedeniyle yaygın olarak araştırılan bir devredir. Bu tez, yeterince geniş bir ayar aralığına ve ince frekans adımlarına sahip, sayısal olarak kontrol edilen bir halka osilatörü önermektedir.
openaire   +1 more source

A Wide-Band Digital Lock-In Amplifier and Its Application in Microfluidic Impedance Measurement. [PDF]

Sensors (Basel), 2019
Huang K, Geng Y, Zhang X, Chen D, Cai Z, Wang M, Zhu Z, Wang Z.   +7 more
europepmc   +1 more source

Three new species of the genus Philopteroides Mey, 2004 (Phthiraptera, Ischnocera, Philopteridae) from New Zealand. [PDF]

Zookeys, 2013
Valim MP, Palma RL.
europepmc   +1 more source