Results 51 to 60 of about 535 (152)

Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

, 2008
An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL
Meganathan D., Praveen Kumar P., J. Raja paul perinbam, Moorthi S., Janarthanan D.   +4 more
core   +1 more source

RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity

, 2018
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li, Donald Y. C. Lie, Chaojiang Li, Dixian Zhao, Christian Fager   +4 more
wiley   +1 more source

Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu, Woogeun Rhee, Zhihua Wang, Sudhakar Pamarti   +3 more
wiley   +1 more source

Modelling and Implementation of an Accumulator-based ADPLL on a Virtex-5

, 2012
In this work, we describe the implementation of an accumulator-based ADPLL on a Virtex 5. The ADPLL includes a Time-to-Digital Converter (TDC) that is based on two delay-lines and an oscillator. The resolution of the TDC is 1ns.
M. Deviato, NAPOLI, ETTORE, E. Napoli, M. P. Kennedy, D. Guerra, M.P. Kennedy, F. Brandonisio, D. Melinn   +7 more
core   +1 more source

A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

IEEE Access, 2023
This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time ...
Abdelrahman G. Habib, Mohamed Dessouky, Ahmed Naguib   +2 more
openaire   +2 more sources

Open‐Loop Wide‐Bandwidth Phase Modulation Techniques

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti, Kenichi Okada   +3 more
wiley   +1 more source

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

IEEE Access
In recent years, frequency-modulated continuous-wave (FMCW) radars have been widely used in the automotive field to measure the relative distance and speed of external targets.
Mengwei Yang, Jinyou Chen, Changhong Shan   +2 more
doaj   +1 more source

A Robust and Efficient Fault-Resilient RadHard ADPLL

International Journal of Systems Applications, Engineering & Development, 2020
The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges.
Varsha Prasad, Sandya Prasad
openaire   +1 more source

A Low‐Power Digitally Controlled Oscillator for All Digital Phase‐Locked Loops

VLSI Design, Volume 2010, Issue 1, 2010., 2010
A low‐power and low‐jitter 12‐bit CMOS digitally controlled oscillator (DCO) design is presented. The Low‐Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters.
Jun Zhao, Yong-Bin Kim, Gregory D. Peterson   +2 more
wiley   +1 more source

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

IEEE Open Journal of the Solid-State Circuits Society
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski   +3 more
doaj   +1 more source