Results 181 to 190 of about 2,220 (245)
Comb‐Driven Coherent Optical Transmitter for Scalable DWDM Interconnects
A comb‐driven coherent optical transmitter on a Si/SiN platform enables scalable DWDM interconnects by integrating ultra‐compact microring‐assisted modulators and interleavers. High‐baud coherent signaling achieves 400 Gb/s per wavelength and >$>$1 Tb/s multi‐channel transmission, with projected >$>$10 Tb/s per fiber, offering a path toward energy ...
Alireza Geravand +11 more
wiley +1 more source
Feasibility of Employing Semi-Hard Magnetic Materials for Hysteresis Magnetic Clutches in Railway Systems. [PDF]
Pistelok P, Adamiak M.
europepmc +1 more source
Research on a Phase-Shift-Based Discontinuous PWM Method for 24V Onboard Thermally Limited Micro Voltage Source Inverters. [PDF]
Wang S, Xia C.
europepmc +1 more source
Highly coherent two-color laser and its application for low-noise microwave generation. [PDF]
He B +10 more
europepmc +1 more source
Excited State Opto-Ionic Reservoir Computing in Hybrid Perovskite Electrochemically-Gated Luminescent Cells. [PDF]
Kollenz P +7 more
europepmc +1 more source
A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops. [PDF]
Guo M, Wang L, Wang S, Lu J, Cui M.
europepmc +1 more source
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
+6 more sources
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
+6 more sources
A Fast-Locking Digital Phase-Locked Loop
Third International Conference on Information Technology: New Generations (ITNG'06), 2006A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results ...
Mahmoud Fawzy Wagdy, Srishti Vaishnava
openaire +1 more source

