Results 11 to 20 of about 375,340 (303)
Electronics Letters, 2022 The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability.
Ryoga Iwashita +3 more
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A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems
IEEE Access, 2022 An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented.
Junghoon Jin, Seungjun Kim, Jongsun Kim
doaj +1 more source
Applied Sciences, 2021 This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system.
Min-Su Kim, Sang-Sun Yoo
doaj +1 more source
IEEE Access, 2021 This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output
Yoonjae Choi +6 more
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A Varactor-Less DCO With
IEEE Access, 2019 The generation of precise linear frequency modulation is a critical requirement for millimeterwave automotive radars. This paper presents the analysis and design of a CMOS 75.5 - 82.5 GHz monotonically linear digitally controlled oscillator (ML-DCO ...
Iman Taha, Mitra Mirhassani
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IEEE Access, 2020 In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is ...
Imran Ali +9 more
doaj +1 more source
Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
core +1 more source
Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS
IEEE Transactions on Nuclear Science, 2022 This article presents a radiation-tolerant digitally controlled complementary metal–oxide–semiconductor (CMOS) ring oscillator design suitable for all-digital phase-locked loop (ADPLL) implementations.
S. Biereigel +4 more
semanticscholar +1 more source
IEEE Access, 2022 This paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock.
Minuk Heo +4 more
doaj +1 more source
CMOS OTA-C high-frequency sinusoidal oscillators [PDF]
, 1991 Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the CMOS OTA's dominant nonidealities.
Huertas Díaz, José Luis +3 more
core +1 more source