Digitally controlled oscillator dco

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Design of a digitally controlled oscillator for an integrated circuit phase-locked loop [PDF]

, 2017
The project focuses on the design and simulation of a digitally-controlled oscillator (DCO) for an all-digital phase-locked loop in a 180nm CMOS process. A ring oscillator with cross-coupled inverter-based delay cells was employed to reduce jitter.
Riaz Ahmad
core

12???14.5 GHZ DIGITALLY CONTROLLED OSCILLATOR USING A HIGH-RESOLUTION DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER [PDF]

, 2020
Department of Electrical EngineeringThis thesis focuses on the design of digitally-controlled oscillators (DCO) for ultra-low-jitter digital phase-locked-loops (PLL), which requires very fine frequency resolution and low phase noise performance.
Jo, Yong-Woo
core

Digitally controlled oscillator를 위한 작은 캐패시턴스가 조절되는 Varactor [PDF]

, 2011
학위논문(석사) - 한국과학기술원 : 정보통신공학과, 2011.2, [ vi, 49 p. ]This thesis reports a novel varactor pairs with small switchable unit capacitance by controlling digital code word.
Choi, Yong-Chang, 최용창
core +2 more sources

A Novel Structure of Digitally Controlled Oscillator for All-Digital Phase-Locked Loop [PDF]

, 2014
本篇論文描述一個應用於全數位鎖相迴路之數位控制振盪器（DCO）的架構與設計，運用新架構的方式，去改善傳統架構數位控制振盪器（DCO）的缺點，使本電路具有較佳的線性度、較好的振盪波形、較小的Jitter，並可振盪出較高的頻率。本新架構之數位控制振盪器（DCO）擁有14-bit的數位控制字元，使用的是TSMC 0.35um 1P4M的製程，操作電壓3V。模擬結果顯示，擁有14-bit的數位控制振盪器（DCO），操作在數位控制字元0 ~ 16383時，頻率範圍為860 MHz ~ 1 ...
Yeh, Chi-Lung, 葉啟龍
core

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]