Results 41 to 48 of about 53 (48)

Trade-off between Hit Rate and Hit Latency for Optimizing DRAM Cache

IEEE Transactions on Emerging Topics in Computing, 2018
Xiaofei Liao, Jianhui Yue, Hai Jin
exaly  

EPUF: An Entropy-Derived Latency-Based DRAM Physical Unclonable Function for Lightweight Authentication in Internet of Things

IEEE Transactions on Mobile Computing
Alessandro Brighente, Mohammad Reza Mosavi, Mauro Conti   +2 more
exaly  

DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Fatemeh Tehranipoor, Fatemeh Tehranipoor   +1 more
exaly  

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

2020
Lois Orosa, Onur Mutlu, Jisung Park
exaly  

Cached DRAM for ILP processor memory access latency reduction

IEEE Micro, 2001
exaly  

Tiered-latency DRAM: A low latency and low cost DRAM architecture

2013
Onur Mutlu, Donghyuk Lee, Vivek Seshadri   +2 more
exaly  

DRAM-Based PUF Utilizing the Variation of Adjacent Cells

IEEE Transactions on Information Forensics and Security
Enas Abulibdeh, Khaled Humood, Baker Mohammad   +2 more
exaly  

FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration

Transactions on Architecture and Code Optimization
Song Chen, Yi Kang, Haitao Du
exaly