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PV Smoothing Duty Cycle

, 2016
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Design of A 0.8GHz-3GHz Duty-Cycle Corrector With a 20%-80% Input Duty Cycle

2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2019
An analog duty cycle correction circuit using a novel pulsewidth modification cell. We correct the duty-cycle by changing the phase of the voltage. Our calibration allows the input duty cycle to range from 20% to 80%, and the circuit corrects the duty cycle to 50%.
Chien Yu Lin, Heng Shou Hsu
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A voltage-controlled duty-cycle oscillator

IEEE Journal of Solid-State Circuits, 1990
A voltage-controlled duty-cycle oscillator (VCDCO) developed for use with integrated silicon sensors is described. The circuit's transfer function is, to first order, completely independent of component values. Measured results indicate that the circuit is capable of resolving input voltage changes as small as 6 mu V in a 2000- mu s period and has a ...
Richard R. Spencer, James B. Angell
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Effects of HiPIMS Duty Cycle on Plasma Discharge and the Properties of Cu Film [PDF]

Materials
Ren Y, Bai H, Liu X, Li J, Liu X.
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Hierarchical Duty-Cycling of Wireless Sensors

2019 28th International Conference on Computer Communication and Networks (ICCCN), 2019
Energy efficiency is critical in many IoT applications with sensors that deliver data over wireless communications. Duty-cycling has been a major method for reducing energy consumption. One popular duty-cycling is MAC duty-cycling where an MCU commands the periodic or adaptive turning on and off of an RF chip.
Jinhwan Jung, Kien Pham, Joohyun Kang, Junehwa Song, Sung-Ju Lee, Yung Yi   +5 more
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Synchronous duty cycle correction circuit

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010
A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of input clock duty cycle, a signal differentiating circuit at the input of the circuit is used which narrows the input duty cycle range to the circuit core.
Sergey Sofer, Valery Neiman, Eyal Melamed-Cohen   +2 more
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Clock buffer with duty cycle corrector

Microelectronics Journal, 2010
A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%.
Shao-Ku Kao, Yong-De You
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