Results 1 to 10 of about 63,886 (186)

A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications [PDF]

Scientific Reports
A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are
Kawther I. Arafa, Dina M. Ellaithy, Heba Shawkey, Mohamed Abouelatta, Abdelhalim Zekry   +4 more
doaj   +2 more sources

Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process [PDF]

International Journal of Electronics and Telecommunications, 2022
This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used.
D. S. Shylu Sam, P. Sam Paul, Diana Jeba Jingle, P. Mano Paul, Judith Samuel, J. Reshma, P. Sarah Sudeepa, G. Evangeline   +7 more
doaj   +1 more source

Design of low power dynamic comparator with reduced kickback noise technique for bio-medical applications

e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023
The latched comparator is an essential element found in all analogue-to-digital converter (ADC) architectures. The present study aims to develop a latched comparator with the objective of mitigating kickback noise.
Pradeep Jinka, Ramashri Tirumala
doaj   +1 more source

Design of a High-Speed and Low Power CMOS Comparator for A/D Converters [PDF]

Journal of Electrical and Computer Engineering Innovations, 2021
Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance.
F. Shakibaee, A. Bijari, S.H. Zahiri
doaj   +1 more source

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

IET Circuits, Devices and Systems, 2022
In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch.
Hamid Mahmoodian, Mehdi Dolatshahi, S. Mohammadali Zanjani, Mohammad Amin Honarvar   +3 more
doaj   +1 more source

Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process. [PDF]

PLoS ONE, 2014
The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher ...
Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali, Mohammad Marufuzzaman   +4 more
doaj   +1 more source

Comparing dynamic causal models

NeuroImage, 2004
This article describes the use of Bayes factors for comparing dynamic causal models (DCMs). DCMs are used to make inferences about effective connectivity from functional magnetic resonance imaging (fMRI) data. These inferences, however, are contingent upon assumptions about model structure, that is, the connectivity pattern between the regions included
Penny, W D, Stephan, K E, Mechelli, A, Friston, K J   +3 more
openaire   +4 more sources

A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS

Electronics Letters, 2021
Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented.
Dengjie Wang, Zeliang Zhao, Ziqiang Wang, Chun Zhang, Zhihua Wang, Hong Chen   +5 more
doaj   +1 more source

Dynamics of Chinese Comparative Advantage [PDF]

SSRN Electronic Journal, 2004
We analyze the dynamics of Chinese comparative advantage as measured by export shares and the Balassa index using 3-digit and 4-digit sectors for the period 1970 ¿ 1997. We use novel tools to identify periods of rapid structural change and the persistence of comparative advantage, such as Galtonian regressions, probability-probability (p-p) plots, and ...
Hinloopen, J., van Marrewijk, C.
openaire   +4 more sources

An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications

Advances in Electrical and Electronic Engineering, 2019
Currently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce
Vikrant Varshney, Rajendra Kumar Nagaria
doaj   +1 more source