Results 51 to 60 of about 64,005 (305)

A Qualitative Analysis of Patient Perspectives and Preferences in Lupus Management to Guide Lupus Guidelines Development

Arthritis Care &Research, EarlyView.
Objective A patient‐centered approach for chronic disease management, including systemic lupus erythematosus (SLE), aligns treatment with patients’ values and preferences, leading to improved outcomes. This paper summarizes how patient experiences, perspectives, and priorities informed the American College of Rheumatology (ACR) 2024 Lupus Nephritis (LN)
Shivani Garg, Izzy Hartel, Lisa R. Sammaritano, Anca Askanase, Bonnie L. Bermas, Maria Dall'Era, Alí Duarte‐García, Victoria P. Werth, Brad Rovin, Reem A. Mustafa, Amy S. Turner, Bené Williams, Brian L. Ung, Hiya Bhavsar, Monique C. Gore‐Massy, Nahirannette Pulido, Natacha Guerrero, Natalie M. Smith, Wambui Machua, Linda T. Hiraki, Mary Beth Son   +20 more
wiley   +1 more source

A CMOS implementation of a spike event coding scheme for analog arrays [PDF]

, 2009
This paper presents a CMOS circuit implementation of a spike event coding/decoding scheme for transmission of analog signals in a programmable analog array. This scheme uses spikes for a time representation of analog signals.
Gouveia, L.C., Hamilton, A., Koickal, T.J.   +2 more
core   +1 more source

Comparator with dynamic hysteresis

Electronics Letters, 1999
A comparator is presented which is based on the use of a time domain phenomenon called 'dynamic hysteresis'. This comparator features only one threshold and a short-time controllable noise immunity.
G. Panov, D. Manova, A. Popov
openaire   +1 more source

Does Long‐Term Lower Extremity Strength Training in Adults With Knee Osteoarthritis and Varus Alignment Reduce Knee Joint Loading During Gait?

Arthritis Care &Research, EarlyView.
Objective We examined whether 18 months of strength training in individuals with knee varus alignment and medial tibiofemoral osteoarthritis (OA) reduced knee joint loads during walking compared to an attention control group. Methods This study was a secondary analysis of a randomized clinical trial that compared the effects of strength training to a ...
Stephen P. Messier, Matthew N. Vigliotti, Paige E. Rice, Brian Pietrosimone, Shannon L. Mihalko, Edward H. Ip, Richard F. Loeser, David J. Hunter, Ali Guermazi, Ryan Hill, Santiago Saldana, Kim L. Bennell, Paul DeVita   +12 more
wiley   +1 more source

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

Sensors, 2022
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology.
Deeksha Verma, Khuram Shehzad, Sung Jin Kim, Young Gun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee   +7 more
doaj   +1 more source

Bio‐Inspired Multimodal Hardware Front‐End Enabled by 2D Floating‐Gate Memory for UAV Perception

Advanced Functional Materials, EarlyView.
A MoS2/h‐BN /graphene floating‐gate memory underpins a bio‐inspired multimodal front end that integrates visual, inertial, and airflow cues. A 4 × 4 FG memory array encodes temporal intensity differences, while IMU‐ and airflow‐driven threshold modulation suppresses self‐motion artifacts, enabling fast, low‐power, robust autonomous UAV tracking and ...
Lianghao Guo, Yue Cheng, Cong Li, Xiaoyu Guo, Jiankai Yin, Dadong Fan, Zhenyu Xu, Chenyu Tang, Arokia Nathan, Shuo Gao, Li Tao, Luigi G. Occhipinti   +11 more
wiley   +1 more source

A 0.9 V high‐speed dynamic bias latch‐type comparator employing a voltage‐controlled delay line

Electronics Letters
This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs).
Feng Tai, Yige Liu, Puyi Bai, Qiang Li
doaj   +1 more source

Design and analysis of optimized dynamic comparator circuit for low-power and high-speed applications

e-Prime: Advances in Electrical Engineering, Electronics and Energy
A typical dynamic comparator consists of two stages: A first stage comprising a differential amplifier and a second stage comprising latch-based circuitry.
Dhandapani Vaithiyanathan, Rajat Mishra, Preeti Verma, Baljit Kaur   +3 more
doaj   +1 more source

A digital phase‐based on‐fly offset compensation method for decision feedback equalisers

IET Circuits, Devices and Systems, 2021
A low‐complexity method to reduce the offset voltage of dynamic comparators employed as samplers in decision feedback equalisers (DFE) is introduced. The authors propose the phase‐domain offset reduction technique (PORT), which leverages an all‐digital ...
Andres Amaya, Javier Ardila, Elkim Roa
doaj   +1 more source

CMOS circuit implementations for neuron models [PDF]

, 1990
The mathematical neuron basic cells used as basic cells in popular neural network architectures and algorithms are discussed. The most popular neuron models (without training) used in neural network architectures and algorithms (NNA) are considered ...
Linares Barranco, Bernabé, Rodríguez Vázquez, Ángel Benito, Sánchez Sinencio, Edgar   +2 more
core   +1 more source