Results 71 to 80 of about 3,165,419 (303)

A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION [PDF]

open access: yes
This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation.
Tani, Sadahiro   +4 more
core   +1 more source

ANALYSIS OF POWER CONSUMPTION SAR-ADC DYNAMIC COMPARATOR [PDF]

open access: yes, 2016
Due to the high demand of ultra-low power in digital application, the needs of energy efficient analog-to-digital converter (ADC) are really essential.
M. Isa, Masnita   +9 more
core   +1 more source

Multimodal Optoelectronic Synapses for Neuromorphic Intelligence: Coupling Light, Electrical, Thermal, and Beyond

open access: yesAdvanced Functional Materials, EarlyView.
This review revisits optoelectronic neuromorphic devices that extend from unimodal sensing toward multimodal perception. Five types of stimuli‐to‐output information flow that are classified based on the device roles within the system and applications are summarized and discussed.
Jihyun Shin   +6 more
wiley   +1 more source

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

open access: yesSensors, 2018
Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques.
Jae-Hun Lee   +5 more
doaj   +1 more source

Emerging Post‐CMOS Hardware Neurons for Brain‐Inspired Computing: Devices, Circuits, and System Integration

open access: yesAdvanced Functional Materials, EarlyView.
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan   +4 more
wiley   +1 more source

A study on propagation delay and power dissipation of a 2-bit CMOS magnitude comparator with critical path evaluation [PDF]

open access: yesE3S Web of Conferences
This work presents the design of 2-bit magnitude comparator in Cadence Virtuoso tool using gpdk090 technology. The detailed analysis of propagation delay and power dissipation (both dynamic and static power) for its outputs—L (A < B), E (A = B), and G (A
Manudeep Tirunagari   +5 more
doaj   +1 more source

Power efficient 64-BIT dynamic comparator using 0.18um technology: article / Mohd Khushairi Mohd Zaidi [PDF]

open access: yes, 2013
This paper presents the comparative study on 64-bit dynamic comparator using different technology. The objective of the paper is to study and compare the speed of the comparator and to compare the power consumption for comparator in 0.5μm and 0.18μm ...
Mohd Zaidi, Mohd Khushairi
core  

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation [PDF]

open access: yes, 2020
Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT ...
Roslina Mohd Sidek   +14 more
core   +1 more source

Atom‐Efficient Cerium‐Based Molecular Cages as Biocompatible Reactive Oxygen Scavengers

open access: yesAdvanced Healthcare Materials, EarlyView.
Discrete mixed‐valent cerium molecular cages organize accessible redox centers within confined coordination environments and scavenge superoxide, hydrogen peroxide, and hydroxyl radicals. Encapsulation of the lead cage in an ROS‐responsive DTP nanoplatform enables lesion‐associated delivery, attenuates macrophage oxidative stress and inflammation, and ...
Chao Li   +9 more
wiley   +1 more source

Neuromorphic Electronics for Intelligence Everywhere: Emerging Devices, Flexible Platforms, and Scalable System Architectures

open access: yesAdvanced Materials, EarlyView.
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj   +8 more
wiley   +1 more source

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