Results 241 to 250 of about 765,447 (285)

Bit Error Floor of MPSK in the Presence of Phase Error

IEEE Transactions on Vehicular Technology, 2016
In mobile communication systems, one of the most significant factors of the bit-error-rate (BER) performance degradation of $M$ -ary phase-shift keying (MPSK) is random phase error caused by phase-locked loop (PLL) or imperfect channel estimation.
Yeonsoo Jang, Jinwoo Jeong, Dongweon Yoon   +2 more
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OFDM error floor based EVM estimation

2016 24th International Conference on Software, Telecommunications and Computer Networks (SoftCOM), 2016
The residual BER - error floor, though useful and widely used metrics for the end-to-end digital radio transmission performance, provides no insight into the error-generating analog impairments (e.g. modulation signal inaccuracy, power amplifier compression, carrier recovery phase error, or I-Q cross- talk), which, however, are easy to identify (so can
Grgić, Mislav, Lipovac, Adriana, Modlic, Borivoj   +2 more
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Error floors and finite geometries

2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), 2014
The structure of certain subgraphs of the Tanner graph of an LDPC code, the trapping sets, has been identified as important for the error floor performance of iterative decoding algorithms. To investigate such sets requires the parity check matrix of the code to be generated with sufficient structure that allows useful information to be obtained while ...
Shu Lin, Qiuju Diao, Ian Blake
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Error floor analysis in LDGM codes

2010 IEEE International Symposium on Information Theory, 2010
Based on discrete density evolution (DDE), we develop closed form expressions to predict the error floor of LDGM codes. The first, rougher, approximation is obtained by assuming perfect message passing between systematic and parity bit nodes in DDE. The second, finer, expression leads to a more involved formulation.
Kejing Liu, Javier Garcia-Frias
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Lowering LDPC Error Floors by Postprocessing

IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference, 2008
A class of combinatorial structures, called absorbing sets, strongly influences the performance of low-density parity-check (LDPC) decoders at low error rates. Past experiments have shown that a class of (8,8) absorbing sets determines the error floor performance of the (2048,1723) Reed-Solomon based LDPC code (RS-LDPC).
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright   +4 more
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Lower the error floor of LDPC with fixed error pattern

2010 International Conference on Educational and Information Technology, 2010
This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern.
null Chen Huang, null Liang Zhou, null Hong Wen, null Qian Zhao, null Fen Xu   +4 more
openaire   +1 more source