Results 251 to 260 of about 128,644 (293)

Non-Binary LDPC Codes for Magnetic Recording Channels: Error Floor Analysis and Optimized Code Design

open access: yesIEEE Transactions on Communications, 2016
© 2016 IEEE.In this paper, we provide a comprehensive analysis of the error floor along with code optimization guidelines for structured and regular non-binary low-density parity-check (NB-LDPC) codes in magnetic recording (MR) applications.
Ahmed Hareedy   +2 more
exaly   +2 more sources

Spatially Coupled Turbo-Like Codes: A New Trade-Off Between Waterfall and Error Floor [PDF]

open access: yesIEEE Transactions on Communications, 2019
Spatially coupled turbo-like codes (SC-TCs) have been shown to have excellent decoding thresholds due to the threshold saturation effect. Furthermore, even for moderate block lengths, the simulation results demonstrate a very good bit error rate ...
Saeedeh Moloudi   +2 more
exaly   +2 more sources

Error floors and finite geometries

2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), 2014
The structure of certain subgraphs of the Tanner graph of an LDPC code, the trapping sets, has been identified as important for the error floor performance of iterative decoding algorithms. To investigate such sets requires the parity check matrix of the code to be generated with sufficient structure that allows useful information to be obtained while ...
Shu Lin 0001, Qiuju Diao, Ian F. Blake
openaire   +1 more source

A survey of error floor of LDPC codes

2011 6th International ICST Conference on Communications and Networking in China (CHINACOM), 2011
The research about error floor of finite-length LDPC code is a very hot topic recently. This survey briefly introduces the existing works in lowering and estimating error floor of LDPC codes, and sheds some light on some potential future research areas.
Yejun He, Jie Yang, Jiawei Song
openaire   +1 more source

Error floor analysis in LDGM codes

2010 IEEE International Symposium on Information Theory, 2010
Based on discrete density evolution (DDE), we develop closed form expressions to predict the error floor of LDGM codes. The first, rougher, approximation is obtained by assuming perfect message passing between systematic and parity bit nodes in DDE. The second, finer, expression leads to a more involved formulation.
Kejing Liu, Javier Garcia-Frías
openaire   +1 more source

Lowering LDPC Error Floors by Postprocessing

IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference, 2008
A class of combinatorial structures, called absorbing sets, strongly influences the performance of low-density parity-check (LDPC) decoders at low error rates. Past experiments have shown that a class of (8,8) absorbing sets determines the error floor performance of the (2048,1723) Reed-Solomon based LDPC code (RS-LDPC).
Zhengya Zhang   +4 more
openaire   +1 more source

On error floor and free distance of turbo codes

ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240), 2002
Turbo codes have excellent performance at low and medium signal-to-noise ratios (SNR) very close to the Shannon limit, and are at the basis of their success. However, a turbo code performance curve can change its slope at high SNR if the code free distance is small.
Roberto Garello   +4 more
openaire   +1 more source

OFDM error floor based EVM estimation

2016 24th International Conference on Software, Telecommunications and Computer Networks (SoftCOM), 2016
The residual BER - error floor, though useful and widely used metrics for the end-to-end digital radio transmission performance, provides no insight into the error-generating analog impairments (e.g. modulation signal inaccuracy, power amplifier compression, carrier recovery phase error, or I-Q cross- talk), which, however, are easy to identify (so can
Adriana Lipovac   +2 more
openaire   +2 more sources

Lower the error floor of LDPC with fixed error pattern

2010 International Conference on Educational and Information Technology, 2010
This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern.
null Chen Huang   +4 more
openaire   +1 more source

On the irreducible error floor in fast fading channels

IEEE Transactions on Vehicular Technology, 2000
In fast fading channels without pilot information, existing receiver structures exhibit an "irreducible error floor," where their bit error rate (BER) levels out at high signal-to-noise ratio (SNR). This is even observed in practical maximum likelihood sequence detectors (i.e., MLSDs with certain approximations, in order to achieve finite per-symbol ...
Brian D. Hart, Desmond P. Taylor
openaire   +1 more source

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