Results 181 to 190 of about 2,049,776 (246)

Characterization and Analysis of RF Switches in SOI Technology for ESD Protection

IEEE International Reliability Physics Symposium, 2022
The self-protection of SOI RF switches is presented in this paper. TLP ESD test results show that the ESD protection performance of SOI RF switches is impacted by various parameters, including switch array gate channel length, finger width, finger number,
Jian Liu, Nathaniel Carels, N. Peachey
semanticscholar   +1 more source

A 4H-SiC MOSFET-Based ESD Protection With Improved Snapback Characteristics for High-Voltage Applications

IEEE transactions on power electronics, 2021
A novel electrostatic discharge (ESD) protection device based on an n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a ...
Kyoung-Il Do, J. Won, Yong-Seo Koo
semanticscholar   +1 more source

A Novel Gate-Controlled Dual Direction SCR With Enhanced Failure Current for On-Chip ESD Protection of Industry-Level Controller Area Network Bus

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2022
The working environment of the industry-level high-voltage communication bus is harsh. Strong electrostatic interference has become one of the key factors affecting the stability of the core module.
Yang Wang, Zeyu Zhong, Xiangliang Jin, Yan-Hua Peng, Jun Luo, Jun Yang   +5 more
semanticscholar   +1 more source

A Dual-MOS-Triggered Silicon-Controlled Rectifier for High-Voltage ESD Protection

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2021
A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such ...
Hailian Liang, Lingzhen Zhu, Xiaofeng Gu
semanticscholar   +1 more source

Internal-Distributed CDM ESD Protection

2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021
CDM ESD protection is a major ESD protection design challenge for advanced ICs, often suffering from random design failures. It was recently reported that the traditional pad-based CDM ESD protection method is fundamentally faulty, contributing to design uncertainties in CDM ESD testing and field failures.
Mengfu Di, Zijin Pan, Cheng Li, Albert Wang   +3 more
openaire   +1 more source

Compact and Low Leakage Devices for Bidirectional Low-Voltage ESD Protection Applications

IEEE Electron Device Letters, 2021
In advanced charged device model (CDM) protection engineering, it is necessary to provide dedicated dual-directional electrostatic discharge (ESD) protection between input/output (I/O) and ground (GND) to discharge the large amount of charge stored in ...
Feibo Du, Yihong Qing, Fei Hou, Kepeng Zou, Wenqiang Song, Ruibo Chen, Jizhi Liu, Le Chen, J. Liou, Zhiwei Liu   +9 more
semanticscholar   +1 more source

Modeling ESD protection

IEEE Potentials, 2005
This work presents the modeling and simulation of ESD circuit design protection. The electrostatic discharge (ESD) is a charge rebalancing process between two adjacent ICs. The ESD can cause IC failure during the manufacturing, the testing, the handling and the assembly of integrated circuits (ICs).
N. Mohan, A. Kumar
openaire   +1 more source

Automotive High-Speed Interfaces: Future Challenges for System-level HV-ESD Protection and First- Time-Right Design

Electrical Overstress/Electrostatic Discharge Symposium, 2021
This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links.
Sergej Bub, M. Mergens, A. Hardock, S. Holland, Ayk Hilbrink   +4 more
semanticscholar   +1 more source

RFCMOS ESD protection and reliability

Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005., 2005
This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for ...
Natarajan, Mahadeva Iyer, Linten, Dimitri, Thijs, S., Jansen, Ph., Tremouilles, D., Jeamsaksiri, Wutthinan, Nakaie, T., Sawada, M., Hasebe, T., Decoutere, S., Groeseneken, G.   +10 more
openaire   +2 more sources

ESD buses for whole-chip ESD protection

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003
A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has more separated power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and ...
null Ming-Dou Ker, null Hun-Hsien Chang, null Tung-Yang Chen   +2 more
openaire   +1 more source