Results 221 to 230 of about 2,049,776 (246)

ESD Protection Design for Open-Drain Power Amplifier in CMOS Technology

IEEE transactions on device and materials reliability, 2019
The on-chip electrostatic discharge (ESD) protection device for radio-frequency (RF) power amplifier (PA) with open-drain structure is studied in this work.
Chun-Yu Lin, Guan-Yi Li
semanticscholar   +1 more source

ESD Challenges in Advanced CMOS Technologies—Designing Diode Based ESD Protection

International Symposium for Testing and Failure Analysis, 2023
Abstract Presentation slides for the ISTFA 2023 Tutorial session “ESD Challenges in Advanced CMOS Technologies-Designing Diode Based ESD Protection.”
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ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains

IEEE transactions on device and materials reliability, 2019
To effectively protect the interface circuit between separated power domains from electrostatic discharge (ESD) damage, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18- $ {\mu }\text{m}$ 1.8-V/3.3-V ...
Jie-Ting Chen, M. Ker
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ESD protection under wire bonding pads

Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396), 2003
We have developed a configuration for diode-based electrostatic discharge structures that can be reliably placed under the metal stack of an integrated circuit wire-bonding pad, thereby reducing the die area consumed for ESD. Prototype structures from both three- and four-level CMOS processes were assembled using gold ball and aluminum wedge bonding ...
W.R. Anderson, W.M. Gonzalez, S.S. Knecht, W. Fowler   +3 more
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Investigation of ESD Protection in SiC BCD Process

IEEE Workshop on Wide Bandgap Power Devices and Applications, 2019
In order to develop electrostatic discharge (ESD) protection structures in Silicon Carbide (SiC) process, the ESD properties of SiC silicon-controlled rectifier (SCR), lateral-diffused MOS (LDMOS) and NMOS devices are reported in this paper.
Pengyu Lai, Hui Wang, A. Abbasi, Sajib Roy, A. Rashid, A. Mantooth, Zhong Chen   +6 more
semanticscholar   +1 more source

Field programmable SONOS ESD protection design

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
This paper reports the first SONOS-based field-programmable ESD protection concept and structure. Prototype in 130nm CMOS demonstrates wide ESD triggering tuning range of ∼2V and ultra low leakage of 1.2pA. It enables post-Si on-chip/in-system ESD design programmability for complex ICs.
J. Liu, Z. T. Shi, X. Wang, H. Zhao, L. Wang, C. Zhang, Z. Dong, L. Lin, A. Wang, Y. Cheng, B. Zhao   +10 more
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Low-Capacitance SCR for On-Chip ESD Protection with High CDM Tolerance in 7nm Bulk FinFET Technology

Electrical Overstress/Electrostatic Discharge Symposium, 2019
A low-capacitance silicon-controlled rectifier for high speed I/O pad protection is implemented with TSMC 7nm bulk FinFET technology. It can achieve much higher ESD robustness per capacitance with better dynamic on-resistance and faster turn-on speed for
Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Yu-Ti Su, Jam-Wem Lee, Kuo-Ji Chen, Ming-Hsiang Song   +6 more
semanticscholar   +1 more source

ESD protection for pHEMT MMIC amplifiers

IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05., 2005
In this paper, we discuss ESD characterization data on typical circuit elements used in GaAs pHEMT MMIC amplifiers. At microwave and mm-wave frequencies, basic circuit performance considerations drive design decisions. Human body model (HBM) data for basic circuit elements can provide guidance for layout and topology trade-offs to improve ESD ...
J.M. Beall, G.I. Drandova
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ESD protection in finfet technologies

IEEE 2011 International SOI Conference, 2011
▸ Strong dependency on - process technology (SOIFF, bulkFF) - process options (strain, SEG,…) - layout parameters (L G , W fin ,…) ▸ ESD needs to be considered early during technology development ▸ ESD remains very challenging but ▸ ESD is no roadblock for the introduction of both SOIFF and bulkFF!
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Schottky LDNMOS for HV ESD protection

2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2017
A simple and useful scheme to improve the ESD performance of HV LDNMOS is reported. Removing the N+ implant from the drain, the silicide to NDDD junction of HV LDNMOS becomes a Schottky barrier. This modification can incorporate a Schottky pnp bipolar into LDNMOS to form an SCR.
Jian-Hsing Lee, Natarajan Mahadeva Iyer, Ruchil Jain, Tsung-Che Tsai   +3 more
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