Results 241 to 250 of about 409,912 (301)

On Fault Identification in Diagnosable Systems

IEEE Transactions on Computers, 1981
This paper begins by giving a characterization of t1/ t1—diagnosable systems. Then a class of t0-diagnosable systems, denoted by d(n,t0,X), is considered. It is shown for any member of this class that: 1) necessary and sufficient conditions for t1/t1—diagnosability are greatly simplified, 2) optimal diagnosis algorithms of time complexity 0(nt0) exist,
Kyung-Yong Chwa, S. Louis Hakimi
openaire   +2 more sources

On-line identification of faults in fault-tolerant imagers

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2006
Detection of defective pixels that develop on-line is a vital part of fault tolerant schemes for repairing imagers during operation. This paper presents a new algorithm for the identification of stuck low, stuck high and partially stuck pixels in both regular and fault tolerant APS systems.
Glenn H. Chapman, Israel Koren, Zahava Koren, Jozsef Dudas, Cory Jung   +4 more
openaire   +1 more source

On-line test for fault-secure fault identification

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
In an increasing number of applications, reliability is essential. On-line resistance to permanent faults is a difficult and important aspect of providing reliability. Particularly vexing is the problem of fault identification. Current methods are either domain specific or expensive.
Samuel Norman Hamilton, Alex Orailoglu
openaire   +1 more source

A parallel fault identification algorithm

Journal of Algorithms, 1990
Summary: Consider a system of n units, at most ...
Edward F. Schmeichel, S. Louis Hakimi, M. Otsuka, Geoff Sullivan   +3 more
openaire   +2 more sources

Identification of redundant delay faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
Various defects during fabrication have been shown in the literature to introduce delay faults in logic circuits. This paper analyzes the effects of these defects on the normal operation of logic circuits with the goal of developing an appropriate model for these faults.
Daniel Brand, Vijay S. Iyengar
openaire   +1 more source

Primitive Path Delay Fault Identification

Proceedings Tenth International Conference on VLSI Design, 1998
We present a novel and efficient method to identify all primitive single and multi path delay faults (PDFs) in multi-level combinational circuits. Our method is the first one to successfully target the primitive PDF identification problem for multi-level circuits-previous research results in this area have been limited either to the identification of ...
Mukund Sivaraman, Andrzej J. Strojwas
openaire   +1 more source

From Fault-Tree To Fault-Identification

IEEE Transactions on Reliability, 1983
Summary: A practical way is given of identifying actual faults, by using a fault tree's complete system of minimal cutsets. For instance, for a fault tree where 20 cutsets are considered with 30 possible primal events, any of them can be found in at most three steps by the proposed FID-algorithm.
openaire   +2 more sources

PARAMETRIC IDENTIFICATION FOR ROBUST FAULT DETECTION

IFAC Proceedings Volumes, 2002
Abstract The work presents some simulation results concerning the application of robust model–based fault diagnosis to an industrial process by using identification and disturbance de–coupling techniques. The first step of the considered approach identifies several equation error models by means of the input–output data acquired from the monitored ...
Fantuzzi C., Simani S.
openaire   +1 more source

Substation fault identification

2010 IEEE International Conference on Industrial Technology, 2010
This paper introduces a new procedure in order to localize and identify a given resistive fault during power system operation. A simple linear identification approach is presented for the ideal noiseless case. For the real noisy situation an algorithm is shown to extract the desired information, allowing to easily identifying buses connected to the ...
Jacques Szczupak, Denis Lage
openaire   +1 more source

Identification of Equivalent Faults in Logic Networks

IEEE Transactions on Computers, 1980
The properties of combinational logic functions and networks that influence equivalence among stuck-type faults are investigated. It is shown that the equivalence of certain types of faults depends only on the function being realized. For instance, the fault classes among primary input/output faults are of this type.
Ayee Goundan, John P. Hayes
openaire   +1 more source