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Information-Theoretic Dual Adaptive Control Revisited: Multivariable Extension with Applications to Fault-Tolerant Control. [PDF]
Yamé JJ.
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Recovery process of a transformer type superconducting fault current limiter
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2014 9th International Conference on Computer Engineering & Systems (ICCES), 2014
Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. Space and safety-critical applications are examples of systems where the principles of fault tolerance and recovery techniques have increasing importance ...
Zdenek Kotásek
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Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. Space and safety-critical applications are examples of systems where the principles of fault tolerance and recovery techniques have increasing importance ...
Zdenek Kotásek
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Recovery with limited replay: fault-tolerant processes in Linda
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing 1990, 2002Research in the area of fault-tolerant distributed systems has focused to a large extent on data surviving various forms of failure. However, in environments where cooperation among processes is important the authors argue that high availability of processes, in addition to their recoverability is crucial.
Srikanth Kambhatla, Jonathan Walpole
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Fault recovery processing in a switching control multiprocessor
Electronics and Communications in Japan (Part I: Communications), 1989AbstractFor a switching system which must operate 24 hours a day with high reliability, the requirements are secure recovery from a fault and minimization of the effect of the fault recovery (i.e., system down time). On the other hand, when a multiprocessor system is employed, competition may be produced among processors, leading to complex and ...
Takahiko Yamada +3 more
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A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip
2011 NORCHIP, 2011A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed.
Khalid Latif 0002 +3 more
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Implementation of image processing applications with evolutionary fault recovery scheme
2014 22nd Iranian Conference on Electrical Engineering (ICEE), 2014This paper presents an evolutionary fault recovery scheme using Evolvable Hardware (EHW) to have reliable computations. The scheme is based on Genetic Algorithm as Evolutionary Algorithm used in EHW and uses Look Up Tables (LUTs) as basic reconfigurable elements.
Elaheh Yadegari, Sied Mehdi Fakhraie
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Fault-tolerant parallel processing with real-time error detection and recovery
[1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers, 2003Presents a unique error recovery mechanism based on new cache states, verified and non-verified, to detect and recover errors produced by the processor or cache memory or both due to transient faults. The scheme remedies the insufficiency of the error-correcting code when faced with processor transient faults.
C.-H. Chen, A.K. Somani
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