Results 241 to 250 of about 919,065 (317)

Fault Diagnosis and Fault Model Aliasing

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005
During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit ...
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy   +2 more
openaire   +1 more source

Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
This article presents a new fault analysis technique against cryptographic devices called the incremental fault analysis (IFA), which can be adapted into fault attacks using more traditional differential fault analysis (DFA) techniques in order to increase their feasibility under more practical fault injection conditions.
Trevor E. Pogue, Nicola Nicolici
openaire   +1 more source

Faults, Injection Methods, and Fault Attacks

IEEE Design & Test of Computers, 2007
An active attacker can induce errors during the computation of the cryptographic algorithm and exploit the faulty results to extract information about the secret key in embedded systems. We call this kind of attack a fault attack. Fault attacks can break an unprotected system more quickly than any other kind of side-channel attack such as simple power ...
Chong Hee Kim, Jean-Jacques Quisquater
openaire   +1 more source

Fault modeling and fault equivalence in CMOS technology

Journal of Electronic Testing, 1991
The need for greater reliability in the fault coverage of test sequences for VLSI circuits has led to the proposal for more accurate fault models and test pattern generation tools. Such improvements bring about a large increase in the fault list to be considered and in the CPU time needed to generate the test.
Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch   +2 more
openaire   +1 more source

Generic Fault Modelling for Fault Injection

2011
Fault injection is a widely used experimental dependability validation method, with a vast amount of techniques and tools. Within the scope of MOGENTES, an EU 7th framework programme project, tools have been developed which implements three different fault injection techniques; hardware-implemented fault injection, software-implemented fault injection ...
Rickard Svenningsson, Henrik Eriksson, Jonny Vinter, Martin Törngren   +3 more
openaire   +1 more source

Fault simulation of unconventional faults in CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator.
Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò   +3 more
openaire   +2 more sources

Flexible Active Power Control of Distributed Power Generation Systems During Grid Faults

IEEE transactions on industrial electronics (1982. Print), 2007
The increasing penetration of distributed power generation into the power system leads to a continuous evolution of grid interconnection requirements. In particular, active power control will play an important role both during grid faults (low-voltage ...
P. Rodríguez, A. Timbus, R. Teodorescu, Marco Liserre, F. Blaabjerg   +4 more
semanticscholar   +1 more source

Fault identification and accommodation for incipient and abrupt faults

2007 46th IEEE Conference on Decision and Control, 2007
This paper proposes a fault tolerant control strategy for failures belonging to a class of functions including both incipient and abrupt faults. To this purpose a sliding mode controller has been designed ensuring the robust boundedness of system trajectories.
PARLANGELI, GIANFRANCO, D. PACELLA, CORRADINI, Maria Letizia   +2 more
openaire   +2 more sources

Combining fault avoidance, fault removal and fault tolerance: an integrated model

14th IEEE International Conference on Automated Software Engineering, 2003
Fault avoidance, fault removal and fault tolerance represent three successive lines of defense against the contingency of faults in software systems and their impact on system reliability. Beyond the colorful discussions of the relative merits of these techniques, the law of diminishing returns advocates that they be used in concert, where each is ...
Ali Mili 0001, Bojan Cukic, T. Xia, Rahma Ben Ayed   +3 more
openaire   +1 more source

From Fault-Tree To Fault-Identification

IEEE Transactions on Reliability, 1983
Summary: A practical way is given of identifying actual faults, by using a fault tree's complete system of minimal cutsets. For instance, for a fault tree where 20 cutsets are considered with 30 possible primal events, any of them can be found in at most three steps by the proposed FID-algorithm.
openaire   +2 more sources